XC5VLX220-1FFG1760C Xilinx Inc, XC5VLX220-1FFG1760C Datasheet - Page 107

• Manufacturer Part Number: XC5VLX220-1FFG1760C
• Description: IC FPGA VIRTEX-5 220K 1760FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX220-1FFG1760C

• Total Ram Bits: 7077888
• Number Of Logic Elements/cells: 221184
• Number Of Labs/clbs: 17280
• Number Of I /o: 800
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1760-BBGA, FCBGA
• No. Of Logic Blocks: 17280
• No. Of Macrocells: 220000
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• No. Of I/o's: 800
• Clock Management: DCM, PLL
• Core Supply: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

X-Ref Target - Figure 3-13
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Matches
1
IBUFG
DCM Driving PLL
2
3
4
5
In some cases precise alignment will not occur because of the difference in loading between
the input capacitance of the external component and the feedback path capacitance of the
FPGA. For example, the external components can have an input capacitance on 1 pF to
4 pF while the FPGA has an input capacitance of around 8 pF. There is a difference in the
signal slope, which is basically skew. Designers need to be aware of this effect to ensure
timing.
The DCM provides an excellent method for generating precision phase-shifted clocks.
However, the DCM cannot reduce the jitter on the reference clock. The PLL can be used to
reduce the output jitter of one DCM clock output. This configuration is shown in
Figure
PLL). The associated waveforms are shown to the right of the block diagram. When the
output of the DCM is used to drive the PLL directly, both DCM and PLL must reside within
the same CMT block. This is the preferred implementation since it produces a minimal
amount of noise on the local, dedicated route. However, a connection can also be made by
connecting the DCM to a BUFG and then to the CLKIN input of a PLL.
CLKIN
CLKFBIN
RST
CLKIN1
CLKFBIN
RST
DCM
PLL
3-13. The PLL is configured to not introduce any phase shift (zero delay through the
CLKFBOUT
CLKFX180
CLK2X180
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
CLK180
CLK270
CLKDV
Figure 3-13: DCM Driving a PLL
CLKFX
CLK2X
CLK90
CLK0
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BUFG
BUFG
6
To Logic, etc.
1
2
3
4
5
6
PLL Use Models
ug190_3_13_092107
107