XC5VLX220-1FFG1760C Xilinx Inc, XC5VLX220-1FFG1760C Datasheet - Page 28

IC FPGA VIRTEX-5 220K 1760FBGA

XC5VLX220-1FFG1760C

Manufacturer Part Number
XC5VLX220-1FFG1760C
Description
IC FPGA VIRTEX-5 220K 1760FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr

Specifications of XC5VLX220-1FFG1760C

Total Ram Bits
7077888
Number Of Logic Elements/cells
221184
Number Of Labs/clbs
17280
Number Of I /o
800
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1760-BBGA, FCBGA
No. Of Logic Blocks
17280
No. Of Macrocells
220000
Family Type
Virtex-5
No. Of Speed Grades
1
No. Of I/o's
800
Clock Management
DCM, PLL
Core Supply
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC5VLX220-1FFG1760C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VLX220-1FFG1760C
Manufacturer:
XILINX
0
Chapter 1: Clock Resources
28
Global Clock Buffer Primitives
The primitives in
Table 1-2: Global Clock Buffer Primitives
BUFGCTRL
The BUFGCTRL primitive shown in
clocks. All other global clock buffer primitives are derived from certain configurations of
BUFGCTRL. The ISE® software tools manage the configuration of all these primitives.
BUFGCTRL has four select lines, S0, S1, CE0, and CE1. It also has two additional control
lines, IGNORE0 and IGNORE1. These six control lines are used to control the input I0 and
I1.
X-Ref Target - Figure 1-1
Notes:
1. All primitives are derived from a software preset of BUFGCTRL.
2. This primitive replaces the BUFGMUX_VIRTEX4 primitive.
BUFGCTRL
BUFG
BUFGCE
BUFGCE_1
BUFGMUX
BUFGMUX_1
BUFGMUX_CTRL
Primitive
(1)
Table 1-2
(2)
www.xilinx.com
Figure 1-1: BUFGCTRL Primitive
are different configurations of the global clock buffers.
Input
I0, I1
I0, I1
I0, I1
I0, I1
I
I
I
IGNORE1
CE1
S1
I1
I0
S0
CE0
IGNORE0
Figure
Output
BUFGCTRL
O
O
O
O
O
O
O
ug190_1_01_032206
1-1, can switch between two asynchronous
CE0, CE1, IGNORE0, IGNORE1, S0, S1
CE
CE
S
S
S
O
Control
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010

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