XC5VLX220-1FFG1760C Xilinx Inc, XC5VLX220-1FFG1760C Datasheet - Page 118

• Manufacturer Part Number: XC5VLX220-1FFG1760C
• Description: IC FPGA VIRTEX-5 220K 1760FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX220-1FFG1760C

• Total Ram Bits: 7077888
• Number Of Logic Elements/cells: 221184
• Number Of Labs/clbs: 17280
• Number Of I /o: 800
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1760-BBGA, FCBGA
• No. Of Logic Blocks: 17280
• No. Of Macrocells: 220000
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• No. Of I/o's: 800
• Clock Management: DCM, PLL
• Core Supply: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4: Block RAM
118
WRITE_FIRST or Transparent Mode (Default)
READ_FIRST or Read-Before-Write Mode
NO_CHANGE Mode
In WRITE_FIRST mode, the input data is simultaneously written into memory and stored
in the data output (transparent write), as shown in
correspond to latch mode when the optional output pipeline register is not used.
X-Ref Target - Figure 4-2
In READ_FIRST mode, data previously stored at the write address appears on the output
latches, while the input data is being stored in memory (read before write). The waveforms
in
used.
X-Ref Target - Figure 4-3
In NO_CHANGE mode, the output latches remain unchanged during a write operation.
As shown in
operation on the same port. These waveforms correspond to latch mode when the optional
output pipeline register is not used.
Figure 4-3
ADDR
ADDR
CLK
CLK
WE
WE
DO
DO
EN
EN
DI
DI
Figure
correspond to latch mode when the optional output pipeline register is not
Disabled
Disabled
0000
0000
4-4, data output remains the last read data and is unaffected by a write
Figure 4-2: WRITE_FIRST Mode Waveforms
Figure 4-3: READ_FIRST Mode Waveforms
XXXX
XXXX
www.xilinx.com
aa
aa
Read
Read
MEM(aa)
MEM(aa)
bb
MEM(bb)=1111
1111
bb
MEM(bb)=1111
1111
Write
Write
old MEM(bb)
1111
Figure
2222
cc
2222
cc
MEM(cc)=2222
MEM(cc)=2222
4-2. These waveforms
Write
Write
old MEM(cc)
2222
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
dd
dd
ug190_4_04_032206
ug190_4_03_032206
XXXX
XXXX
Read
Read
MEM(dd)
MEM(dd)