XC4VFX100-10FFG1517I Xilinx Inc, XC4VFX100-10FFG1517I Datasheet - Page 346

• Manufacturer Part Number: XC4VFX100-10FFG1517I
• Description: IC FPGA VIRTEX-4FX 100K 1517FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX100-10FFG1517I

• Number Of Logic Elements/cells: 94896
• Number Of Labs/clbs: 10544
• Total Ram Bits: 6930432
• Number Of I /o: 768
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 7: SelectIO Logic Resources
346
Location Constraints
Each IDELAYCTRL module has XY location coordinates (X:row, Y:column). To constrain
placement, IDELAYCTRL instances can have LOC properties attached to them. The
naming convention for IDELAYCTRL placement coordinates is different from the
convention used in naming CLB locations. This allows LOC properties to transfer easily
from array to array.
There are two methods of attaching LOC properties to IDELAYCTRL instances.
1.
2.
Inserting LOC Constraints in a UCF File
The following syntax is used for inserting LOC constraints in a UCF file.
Embedding LOC Constraints Directly into HDL Design Files
The following syntax is used to embed LOC constraints into a Verilog design file.
In VHDL code, the LOC constraint is described with VHDL attributes. Before it can be
used, the constraint must be declared with the following syntax:
Once declared, the LOC constraint can be specified as:
This section describes the VHDL and Verilog use models for instantiating IDELAYCTRL
primitives with LOC constraints.
VHDL Use Model
Insert LOC constraints in a UCF file
Embed LOC constraints directly into HDL design files
INST "instance_name" LOC=IDELAYCTRL_X#Y#;
// synthesis attribute loc of instance_name is "IDELAYCTRL_X#Y0#";
attribute loc : string;
attribute loc of instance_name:label is "IDELAYCTRL_X#Y0#";
-- Multiple instances of IDELAYCTRL primitives are instantiated.
-- Each instance has its own RST and RDY signal to allow for partial
-- reconfiguration.
-- The REFCLK signal is common to all instances
dlyctrl_1:IDELAYCTRL
dlyctrl_2:IDELAYCTRL
.
.
.
dlyctrl_n:IDELAYCTRL
port map(
port map(
port map(
www.xilinx.com
);
);
RDY => rdy _1,
REFCLK => refclk,
RST => rst_1
RDY => rdy _2,
REFCLK => refclk,
RST => rst_2
RDY => rdy _n,
REFCLK => refclk,
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
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