XC4VFX100-10FFG1517I Xilinx Inc, XC4VFX100-10FFG1517I Datasheet - Page 206

• Manufacturer Part Number: XC4VFX100-10FFG1517I
• Description: IC FPGA VIRTEX-4FX 100K 1517FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX100-10FFG1517I

• Number Of Logic Elements/cells: 94896
• Number Of Labs/clbs: 10544
• Total Ram Bits: 6930432
• Number Of I /o: 768
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 5: Configurable Logic Blocks (CLBs)
Table 5-5: General Slice Timing Parameters (Continued)
206
T
T
Sequential Delays
T
T
Setup and Hold for Slice Sequential Elements
T
T
T
T
T
T
Set/Reset
TRPW
TRQ
FTOG
IF6Y
INAFX
CKO
CKLO
xxCK
CKxx
DICK
FXCK
CECK
SRCK
Parameter
/T
/T
/T
= Setup time (before clock edge)
= Hold time (after clock edge)
/T
/T
CKDI
CKSR
CKFX
CKCE
INBFX
F
YMUX output
F
output
FF Clock (CLK) to XQ/YQ
outputs
Latch Clock (CLK) to
XQ/YQ outputs
BX/BY Inputs
F
CE input
SR/BY inputs
XINA
XINA
XINA
/F
/F
/F
XINB
XINB
XINB
Function
inputs to
inputs to FX
Input
Propagation delay from the F
the YMUX output of the slice.
Propagation delay from the F
the FX output of the slice.
Time after the clock that data is stable at the XQ/YQ outputs of the
slice sequential elements (configured as a flip-flop).
Time after the clock that data is stable at the XQ/YQ outputs of the
slice sequential elements (configured as a latch).
Time before Clock (CLK) that data from the BX or BY inputs of the
slice must be stable at the D-input of the slice sequential elements
(configured as a flip-flop).
Time before Clock (CLK) that data from the F
the slice must be stable at the D-input of the slice sequential elements
(configured as a flip-flop).
Time before Clock (CLK) that the CE (Clock Enable) input of the slice
must be stable at the CE-input of the slice sequential elements
(configured as a flip-flop).
Time before Clock (CLK) that the SR (Set/Reset) and the BY (Rev)
inputs of the slice must be stable at the SR/Rev-inputs of the slice
sequential elements (configured as a flip-flop). Synchronous
set/reset only.
Minimum Pulse Width for the SR (Set/Reset) and BY (Rev) pins.
Propagation delay for an asynchronous Set/Reset of the slice
sequential elements. From SR/BY inputs to XQ/YQ outputs.
Toggle Frequency - Maximum Frequency that a CLB flip-flop can be
clocked: 1/(T
www.xilinx.com
CH
+T
CL
).
Description
XINA
XINA
/F
/F
XINB
XINB
UG070 (v2.6) December 1, 2008
inputs, through F6MUX to
inputs, through F6MUX to
Virtex-4 FPGA User Guide
XINA
or F
XINB
inputs of
R