XC4VFX100-10FFG1517I Xilinx Inc, XC4VFX100-10FFG1517I Datasheet - Page 329

• Manufacturer Part Number: XC4VFX100-10FFG1517I
• Description: IC FPGA VIRTEX-4FX 100K 1517FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX100-10FFG1517I

• Number Of Logic Elements/cells: 94896
• Number Of Labs/clbs: 10544
• Total Ram Bits: 6930432
• Number Of I /o: 768
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
ILOGIC Timing Models
R
ILOGIC Timing Characteristics
This section describes the timing associated with the various resources within the ILOGIC
block.
Figure 7-9
T
Clock Event 1
•
•
CLK
CE1
IDOCKD
SR
Q1
D
endmodule;
//Example IDDR instantiation
IDDR U_IDDR (
.Q1(user_q1),
.Q2(user_q2),
.C(user_c),
.CE(user_ce),
.D(user_d),
.R(user_r),
.S(user_s)
);
At time T
High at the CE1 input of the input register, enabling the input register for incoming
data.
At time T
input of the input register and is reflected on the Q1 output of the input register at
time T
.
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
parameter INIT_Q1 = 1'b0;
parameter INIT_Q2 = 1'b0;
parameter SRTYPE = "SYNC";
illustrates ILOGIC register timing. When IDELAY is used, T
ICKQ
ICE1CK
IDOCK
Figure 7-9: ILOGIC Input Register Timing Characteristics
after Clock Event 1.
1
before Clock Event 1, the input signal becomes valid-High at the D
before Clock Event 1, the input clock enable signal becomes valid-
T
T
IDOCK
ICE1CK
www.xilinx.com
T
ICKQ
2
3
4
T
ISRCK
IDOCK
ILOGIC Resources
T
ICKQ
is replaced by
ug070_7_09_072904
5
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