XC3S50AN-4TQG144I Xilinx Inc, XC3S50AN-4TQG144I Datasheet - Page 83

• Manufacturer Part Number: XC3S50AN-4TQG144I
• Description: IC FPGA SPARTAN-3AN50K 144-TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S50AN-4TQG144I

• Total Ram Bits: 55296
• Number Of Logic Elements/cells: 1584
• Number Of Labs/clbs: 176
• Number Of I /o: 108
• Number Of Gates: 50000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 144-LQFP
• No. Of Logic Blocks: 176
• No. Of Gates: 50000
• No. Of Macrocells: 1584
• Family Type: Spartan-3AN
• No. Of Speed Grades: 4
• No. Of I/o's: 108
• Clock: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1597; XC3S50AN-4TQG144I

Table 70: Spartan-3AN FTG256 Pinout (XC3S50AN, XC3S200AN, XC3S400AN) (Cont’d)
DS557 (v4.1) April 1, 2011
Product Specification
Bank
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IP_2
IP_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
IO_L01N_3
IO_L01P_3
IO_L02N_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
N.C.
N.C.
N.C.
N.C.
IO_L08N_3/VREF_3
IO_L08P_3
N.C.
N.C.
N.C.
N.C.
IO_L11N_3/LHCLK1
IO_L11P_3/LHCLK0
IO_L12N_3/IRDY2/LHCLK3
IO_L12P_3/LHCLK2
IO_L14N_3/LHCLK5
IO_L14P_3/LHCLK4
IO_L15N_3/LHCLK7
IO_L15P_3/TRDY2/LHCLK6
N.C.
N.C.
N.C.
N.C.
XC3S50AN Pin Name
www.xilinx.com
IP_2
IP_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
IO_L01N_3
IO_L01P_3
IO_L02N_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
IO_L05N_3
IO_L05P_3
IO_L07N_3
IO_L07P_3
IO_L08N_3/VREF_3
IO_L08P_3
IO_L09N_3
IO_L09P_3
IO_L10N_3
IO_L10P_3
IO_L11N_3/LHCLK1
IO_L11P_3/LHCLK0
IO_L12N_3/IRDY2/LHCLK3
IO_L12P_3/LHCLK2
IO_L14N_3/LHCLK5
IO_L14P_3/LHCLK4
IO_L15N_3/LHCLK7
IO_L15P_3/TRDY2/LHCLK6
IO_L16N_3
IO_L16P_3/VREF_3
IO_L17N_3
IO_L17P_3
XC3S200AN/XC3S400AN Pin Name
Spartan-3AN FPGA Family: Pinout Descriptions
FTG256 Ball
M11
R12
L10
M7
M8
N5
M9
R4
R8
C1
C2
D3
D4
D1
G4
G1
G3
H1
G2
H3
E1
E2
E3
F3
F1
H4
H5
H6
K1
K3
L7
L8
L9
J3
J1
J2
L2
L1
J6
J4
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
INPUT
INPUT
VCCO
VCCO
VCCO
VCCO
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
83