XC3S50AN-4TQG144I Xilinx Inc, XC3S50AN-4TQG144I Datasheet - Page 37

• Manufacturer Part Number: XC3S50AN-4TQG144I
• Description: IC FPGA SPARTAN-3AN50K 144-TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S50AN-4TQG144I

• Total Ram Bits: 55296
• Number Of Logic Elements/cells: 1584
• Number Of Labs/clbs: 176
• Number Of I /o: 108
• Number Of Gates: 50000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 144-LQFP
• No. Of Logic Blocks: 176
• No. Of Gates: 50000
• No. Of Macrocells: 1584
• Family Type: Spartan-3AN
• No. Of Speed Grades: 4
• No. Of I/o's: 108
• Clock: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1597; XC3S50AN-4TQG144I

Three-State Output Propagation Times
Table 28: Timing for the IOB Three-State Path
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
2.
Synchronous Output Enable/Disable Times
T
T
Asynchronous Output Enable/Disable Times
T
Set/Reset Times
T
T
IOCKHZ
IOCKON
GTS
IOSRHZ
IOSRON
Symbol
The numbers in this table are tested using the methodology presented in
Table 10
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the
data Output. When this is true, add the appropriate Output adjustment from
(2)
(2)
and
Time from the active transition at the OTCLK
input of the Three-state Flip-Flop (TFF) to when
the Output pin enters the high-impedance state
Time from the active transition at TFF’s OTCLK
input to when the Output pin drives valid data
Time from asserting the Global Three State
(GTS) input on the STARTUP_SPARTAN3A
primitive to when the Output pin enters the
high-impedance state
Time from asserting TFF’s SR input to when the
Output pin enters a high-impedance state
Time from asserting TFF’s SR input at TFF to
when the Output pin drives valid data
Table
13.
Description
www.xilinx.com
Spartan-3AN FPGA Family: DC and Switching Characteristics
LVCMOS25, 12 mA
output drive, Fast slew
rate
LVCMOS25, 12 mA
output drive, Fast slew
rate
LVCMOS25, 12 mA
output drive, Fast slew
rate
Conditions
Table 30
Table
29.
and are based on the operating conditions set forth in
Device
All
All
All
All
All
Speed Grade
Max
0.63
2.80
9.47
1.61
3.57
-5
10.36
Max
0.76
3.06
1.86
3.82
-4
Units
ns
ns
ns
ns
ns
37