XC3S50-4VQG100I Xilinx Inc, XC3S50-4VQG100I Datasheet - Page 95

• Manufacturer Part Number: XC3S50-4VQG100I
• Description: SPARTAN-3A FPGA 50K STD 100-VQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S50-4VQG100I

• Total Ram Bits: 73728
• Number Of Logic Elements/cells: 1728
• Number Of Labs/clbs: 192
• Number Of I /o: 63
• Number Of Gates: 50000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 100-TQFP
• No. Of Logic Blocks: 192
• No. Of Gates: 50000
• No. Of Macrocells: 1728
• Family Type: Spartan-3
• No. Of Speed Grades: 4
• No. Of I/o's: 63
• Clock Management: DLL
• Package: 100VTQFP
• Family Name: Spartan®-3
• Device Logic Units: 1728
• Device System Gates: 50000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 63
• Ram Bits: 73728
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 66: Timing for the Master and Slave Parallel Configuration Modes (Continued)
DS099-3 (v2.5) December 4, 2009
Product Specification
98
Notes:
1.
2.
3.
4.
Hold Times
T
T
T
Clock Timing
T
T
F
ΔF
SMCCD
SMCCCS
SMWCC
CCH
CCL
CCPAR
Symbol
CCPAR
The numbers in this table are based on the operating conditions set forth in
RDWR_B is synchronized to CCLK for the purpose of performing the Abort operation. The same pin asynchronously controls the
driver impedance of the D0 - D7 pins. To avoid contention when writing configuration data to the D0 - D7 bus, do not bring RDWR_B
High when CS_B is Low.
In the Slave Parallel mode, it is necessary to use the BUSY pin when the CCLK frequency exceeds this maximum specification.
Some Xilinx documents may refer to Parallel modes as "SelectMAP" modes.
(2)
R
The time from the rising transition at the CCLK pin to the point
when data is last held at the D0-D7 pins
The time from the rising transition at the CCLK pin to the point
when a logic level is last held at the CS_B pin
The time from the rising transition at the CCLK pin to the point
when a logic level is last held at the RDWR_B pin
CCLK input pin High pulse width
CCLK input pin Low pulse width
Frequency of the
clock signal at the
CCLK input pin
Variation from the CCLK output frequency set using the BitGen
option ConfigRate
No bitstream
compression
With bitstream compression
During STARTUP phase
Description
Spartan-3 FPGA Family: DC and Switching Characteristics
www.xilinx.com
Not using the BUSY pin
Using the BUSY pin
Table
31.
(3)
Master
Master
Slave/
Slave
Both
All Speed Grades
–50%
Min
0
0
0
5
0
0
0
5
0
+50%
Max
50
66
20
50
∞
∞
-
-
-
Units
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
-
95