XC3S50-4VQG100I Xilinx Inc, XC3S50-4VQG100I Datasheet - Page 33

• Manufacturer Part Number: XC3S50-4VQG100I
• Description: SPARTAN-3A FPGA 50K STD 100-VQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S50-4VQG100I

• Total Ram Bits: 73728
• Number Of Logic Elements/cells: 1728
• Number Of Labs/clbs: 192
• Number Of I /o: 63
• Number Of Gates: 50000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 100-TQFP
• No. Of Logic Blocks: 192
• No. Of Gates: 50000
• No. Of Macrocells: 1728
• Family Type: Spartan-3
• No. Of Speed Grades: 4
• No. Of I/o's: 63
• Clock Management: DLL
• Package: 100VTQFP
• Family Name: Spartan®-3
• Device Logic Units: 1728
• Device System Gates: 50000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 63
• Ram Bits: 73728
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The DLL component has two clock inputs, CLKIN and
CLKFB, as well as seven clock outputs, CLK0, CLK90,
CLK180, CLK270, CLK2X, CLK2X180, and CLKDV as
described in
neously; however, the High Frequency mode only supports
Table 15: DLL Signals
The clock signal supplied to the CLKIN input serves as a
reference waveform, with which the DLL seeks to align the
feedback signal at the CLKFB input. When eliminating clock
skew, the common approach to using the DLL is as follows:
The CLK0 signal is passed through the clock distribution
network to all the registers it synchronizes. These registers
are either internal or external to the FPGA. After passing
through the clock distribution network, the clock signal
returns to the DLL via a feedback line called CLKFB. The
control block inside the DLL measures the phase error
between CLKFB and CLKIN. This phase error is a measure
of the clock skew that the clock distribution network intro-
DS099-2 (v2.5) December 4, 2009
Product Specification
CLKIN
CLKFB
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
Signal
R
Table
Direction
Output
Output
Output
Output
Output
Output
Output
Input
Input
15. The clock outputs drive simulta-
Accepts original clock signal.
CLK_FEEDBACK attribute accordingly).
Generates clock signal with same frequency and phase as CLKIN.
Generates clock signal with same frequency as CLKIN, only
phase-shifted 90°.
Generates clock signal with same frequency as CLKIN, only
phase-shifted 180°.
Generates clock signal with same frequency as CLKIN, only
phase-shifted 270°.
Generates clock signal with same phase as CLKIN, only twice the
frequency.
Generates clock signal with twice the frequency of CLKIN,
phase-shifted 180° with respect to CLKIN.
Divides the CLKIN frequency by CLKDV_DIVIDE value to generate
lower frequency clock signal that is phase-aligned to CLKIN.
Accepts either CLK0 or CLK2X as feed back signal. (Set
Description
www.xilinx.com
a subset of the outputs available in the Low Frequency
mode. See
initialize and report the state of the DLL are discussed in
The Status Logic Component, page
duces. The control block activates the appropriate number
of delay elements to cancel out the clock skew. Once the
DLL has brought the CLK0 signal in phase with the CLKIN
signal, it asserts the LOCKED output, indicating a “lock” on
to the CLKIN signal.
DLL Attributes and Related Functions
A number of different functional options can be set for the
DLL component through the use of the attributes described
in
tions that follow:
Table
Spartan-3 FPGA Family: Functional Description
16. Each attribute is described in detail in the sec-
DLL Frequency Modes, page
Frequency
Low
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Mode Support
40.
35. Signals that
Frequency
High
Yes
Yes
Yes
Yes
Yes
No
No
No
No
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