XC3S50-4VQG100I Xilinx Inc, XC3S50-4VQG100I Datasheet - Page 84

SPARTAN-3A FPGA 50K STD 100-VQFP

XC3S50-4VQG100I

Manufacturer Part Number
XC3S50-4VQG100I
Description
SPARTAN-3A FPGA 50K STD 100-VQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3r
Datasheet

Specifications of XC3S50-4VQG100I

Total Ram Bits
73728
Number Of Logic Elements/cells
1728
Number Of Labs/clbs
192
Number Of I /o
63
Number Of Gates
50000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
100-TQFP
No. Of Logic Blocks
192
No. Of Gates
50000
No. Of Macrocells
1728
Family Type
Spartan-3
No. Of Speed Grades
4
No. Of I/o's
63
Clock Management
DLL
Package
100VTQFP
Family Name
Spartan®-3
Device Logic Units
1728
Device System Gates
50000
Maximum Internal Frequency
630 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
63
Ram Bits
73728
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC3S50-4VQG100I
Manufacturer:
XILINX
Quantity:
750
Part Number:
XC3S50-4VQG100I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S50-4VQG100I
Manufacturer:
XILINX
0
Company:
Part Number:
XC3S50-4VQG100I
Quantity:
700
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 53: Synchronous 18 x 18 Multiplier Timing
Table 54: Asynchronous 18 x 18 Multiplier Timing
84
Notes:
1.
Notes:
1.
Clock-to-Output Times
T
Setup Times
T
Hold Times
T
Propagation Times
T
MULTCK
MULIDCK
MULCKID
MULT
Symbol
The numbers in this table are based on the operating conditions set forth in
The numbers in this table are based on the operating conditions set forth in
Symbol
When reading from the
Multiplier, the time from the
active transition at the C
clock input to data
appearing at the P outputs
Time from the setup of data
at the A and B inputs to the
active transition at the C
input of the Multiplier
Time from the active
transition at the Multiplier’s
C input to the point where
data is last held at the A
and B inputs
The time it takes for data to travel from the A and B
inputs to the P outputs
Description
Description
P Outputs
P[15]
P[17]
P[19]
P[23]
P[31]
P[35]
P[0]
-
-
www.xilinx.com
1.84
Min
0
-
-
-
-
-
-
-
-5
Table
Table
P Outputs
P[15]
P[17]
P[19]
P[23]
P[31]
P[35]
Max
1.00
1.15
1.30
1.45
1.76
2.37
2.67
P[0]
Speed Grade
-
-
31.
31.
2.11
Min
0
-
-
-
-
-
-
-
Max
1.55
3.15
3.36
3.49
3.73
4.23
4.47
-5
DS099-3 (v2.5) December 4, 2009
Speed Grade
-4
Max
1.15
1.32
1.50
1.67
2.02
2.72
3.07
Product Specification
Max
1.78
3.62
3.86
4.01
4.29
4.86
5.14
-
-
-4
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R

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