EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 9

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Stratix IV E ES Device Issues
March 2011 Altera Corporation
High I/O Pin Leakage Current
Higher Standby Current for V
Reduced M9K/M144K Performance
DPA Misalignment
Top and bottom I/O pin leakage current is higher for Stratix IV E ES devices than
production devices. Side I/O banks are not affected. Refer to
ES device I/O pin leakage current on top and bottom I/O banks.
Table 4. I/O Pin Leakage Current for Top and Bottom I/O Banks
These I/O pin leakage current values apply to ES silicon only and not to production
silicon.
You can expect to see higher standby I
Stratix IV E ES devices than indicated in the Quartus II software version 9.0 and the
Stratix IV E PowerPlay EPE version 9.0. The higher standby I
power supply is fixed in production devices.
Use the Stratix IV E PowerPlay EPE version 9.0.1 to estimate current and
power/thermal requirements for the Stratix IV E ES device. The Stratix IV E
PowerPlay EPE version 9.0 will not be updated with these higher standby current
values.
M9K/M144K f
than indicated in the Quartus II software version 8.1. Compile your design in the
Quartus II software version 9.0 to estimate the impact on your design.
Stratix IV E DPA circuitry for ES devices occasionally become stuck at the initial
configured phase or take significantly longer than expected to select the optimum
phase. A non-ideal phase may result in data bit errors, even after the DPA lock signal
has gone high. Resetting the DPA circuit may not alleviate the problem; in fact,
resetting it might trigger the problem. LVDS receivers configured in DPA mode are
affected. LVDS receivers configured in Soft CDR mode with 0 PPM difference
(synchronous interface) are also affected.
For applications with flexibility in the choice of training patterns, Altera recommends
you choose bit sequences with more data transitions and a non-cyclical pattern similar
to a PRBS or K28.5 code sequence.
For applications using a fixed, cyclical, or data transition sparse training pattern (for
example, if you are using the SPI 4.2 protocol, which specifies a training pattern of ten
0s and ten 1s), turn on the DPA PLL Calibration feature (available in the Quartus II
software version 9.0) in the ALTLVDS MegaWizard Plug-In Manager.
Temperature
25°C
85°C
MAX
140
3.0
35
and t
CO
CC
performance for Stratix IV E ES devices may be lower
Power Supply
100
2.5
25
I/O Bank Voltage (V)
CC
values on the V
1.8
15
60
1.5
11
45
CC
power supply for
Errata Sheet for Stratix IV E Devices
CC
Table 4
current for the V
1.2
35
9
for Stratix IV E
Units
μA
μA
Page 9
CC