EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 2

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Page 2
Errata Sheet for Stratix IV E Devices
I/O Jitter
Fast Passive Parallel (FPP) Mode Configuration Failures at High DCLK
Frequency
FPP Mode Configuration Failures When the Minimum Hold Time (t
to 0 ns or 24 ns
f
Affected Stratix IV E production devices (refer to
higher than expected jitter on general purpose I/O pins. I/O pins in LVDS mode
(including dynamic phase alignment [DPA] and soft clock data recovery [CDR]) are
not affected. The actual amount of additional jitter depends on the device switching
activity.
The EP4SE230 production ordering code is not affected.
Altera is fixing this issue in the next revision of production devices, which will meet
all current jitter specifications.
For further support, file a service request using mysupport.altera.com.
Stratix IV E devices might fail to configure in FPP mode if the DCLK frequency is set
to 125 MHz with 60/40 or 40/60 duty cycle. When this issue occurs, the device pulls
the nSTATUS pin low and the configuration host may initiate a reconfiguration.
This problem affects all Stratix IV E devices.
For successful FPP configuration at 125 MHz for devices with the density of the
EP4SE360 and lower, set the duty cycle to 45/55, 55/45, or higher. This corresponds to
a minimum DCLK high time (t
For EP4SE530 devices, reduce the DCLK frequency to 100 MHz or lower and set the
duty cycle to 45/55, 55/45, or higher. This corresponds to a minimum DCLK high
time (t
For EP4SE820 devices, reduce the DCLK frequency to 80 MHz or lower and set the
duty cycle to 45/55, 55/45, or higher. This corresponds to a minimum DCLK high
time (t
Stratix IV E devices might fail to configure in FPP mode if the minimum hold time
(t
configuration data, or 24 ns for compressed and/or encrypted data. When this issue
occurs, the device pulls the nSTATUS pin low and the configuration host may initiate a
reconfiguration.
This problem affects all Stratix IV E devices.
You can successfully configure the Stratix IV E devices in FPP mode by setting the
minimum hold time (t
to 1 ns or higher. For compressed and/or encrypted data, set the minimum hold time
(t
Alternatively, you can drive the configuration data out on the falling edge of the
DCLK.
DH
DH
) for the configuration data is set to 0 ns for uncompressed and unencrypted
) to 3 * 1/f
CH
CH
) and a minimum DCLK low time (t
) and a minimum DCLK low time (t
DCLK
+ 1 ns or higher (f
DH
) for the uncompressed and unencrypted configuration data
CH
) and a minimum DCLK low time (t
DCLK
is your DCLK frequency setting).
CL
CL
) of 4.5 ns.
) of 5.6 ns.
Production Device Issues for Stratix IV E Devices
Table
1) may exhibit up to ±50 ps
March 2011 Altera Corporation
CL
) of 3.6 ns.
DH
) is set