EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 8

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Page 8
Errata Sheet for Stratix IV E Devices
Higher V
I/O Jitter
Higher Minimum f
f
CC
Stratix IV E ES devices require higher V
Table 3. Power Supply Levels for Stratix IV E ES Devices
EP4SE530 ES devices require V
V for all speed grades.
Use the Stratix IV E PowerPlay EPE version 9.0.1 to estimate current and
power/thermal requirements for Stratix IV E ES devices with the required higher
power supply levels. The Stratix IV E PowerPlay EPE version 9.0 reflects current and
power estimates for production devices at data sheet specifications only.
Production devices will not operate at these higher power supply levels. If needed,
design your power supplies to support dropping power supply levels back to data
sheet specification for production devices.
There are no reliability issues with Stratix IV E ES devices at these higher power
supply levels.
Stratix IV E ES devices may exhibit ± ~100 ps higher than expected jitter on all I/O
pins. The actual amount of additional jitter is application and toggle-rate dependent.
Altera fixed the issue in production devices, which meets all current jitter
specifications.
If you are using ES devices, you need to account for this additional timing uncertainty
in all I/O timing closure budgets.
Stratix IV E ES devices may exhibit higher than expected PLL jitter at low f
settings. Raising the minimum f
ES devices.
Altera fixed the issue in production devices, which meets the current f
of 5 MHz.
If you are using ES devices, review your f
PFD Frequency” in each PLL section of your .fit.rpt compilation report file. If needed,
recompile your design in the Quartus II software with modified PLL settings to
achieve the higher minimum f
For more information about the ALTPLL megafunction, refer to the
Handbook
Power Supply
Power Supply Levels
V
CCD_PLL
V
CC
or the
INPFD
Phase-Locked Loops (ALTPLL) Megafunction User
Power Supply Level (V)
Setting
0.95
0.95
IN PFD
CC
INPFD
and V
.
to 25 MHz removes the additional PLL jitter in
CC
CCD_PLL
Core voltage and periphery circuitry power supply
PLL digital power supply
INPFD
power supply levels (refer to
settings by searching under “Nominal
power supplies set to 0.95 V +/- 0.03
Description
March 2011 Altera Corporation
Guide.
Stratix IV E ES Device Issues
Quartus II
INPFD
Table
IN PFD
minimum
3).