EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 66
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EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
1–58
Figure 1–6. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate Less than 1.25 Gbps
Table 1–45. DLL Frequency Range Specifications for Stratix IV Devices—Preliminary (Part 1 of 2)
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
Frequency
Mode
0
1
2
3
4
5
6
0.1 UI
Sinusoidal Jitter Amplitude
P-P
Speed Grade
120-180
150-220
180-280
240-350
290-430
360-540
–2/–2×
90-140
Table 1–44
data rate equal to or higher than 1.25 Gbps.
Table 1–44. LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate Equal to or Higher
than 1.25 Gbps
Figure 1–6
a data rate less than 1.25 Gbps.
DLL and DQS Logic Block Specifications
Table 1–45
Frequency Range (MHz)
Speed Grade
shows the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for
lists the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for a
lists the DLL frequency range specifications for Stratix IV devices.
120-170
150-210
180-260
240-320
290-380
360-450
F1
F2
F3
F4
90-130
–3
Jitter Frequency (Hz)
20db/dec
Speed Grade
120-160
150-200
180-240
240-290
290-360
360-450
90-120
–4
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
baud/1667
50,000,000
1,493,000
Available Phase Shift
22.5°, 45°, 67.5°, 90°
36°, 72°, 108°, 144°
36°, 72°, 108°, 144°
45°, 90°, 135°, 180°
45°, 90°,135°, 180°
10,000
17,565
30°, 60°, 90°, 120°
30°, 60°, 90°, 120°
20 MHz
DQS Delay Buffer
Sinusoidal Jitter (UI)
Mode
April 2011 Altera Corporation
High
High
High
Low
Low
Low
Low
Switching Characteristics
25.000
25.000
(1)
0.350
0.350
Frequency
Number of
Chains
Delay
16
12
10
12
10
8
8