EP1S40B956C6 Altera, EP1S40B956C6 Datasheet - Page 92
![IC STRATIX FPGA 40K LE 956-BGA](/photos/6/73/67334/544-stratix_956-bga_sml.jpg)
EP1S40B956C6
Manufacturer Part Number
EP1S40B956C6
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S40B956C6
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1423
EP1S40SB956C6
EP1S40SB956C6
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PLLs & Clock Networks
2–78
Stratix Device Handbook, Volume 1
Figure 2–45. EP1S30 Device Fast Regional Clock Pin Connections to Fast
Regional Clocks
Notes to
(1)
(2)
Combined Resources
Within each region, there are 22 distinct dedicated clocking resources
consisting of 16 global clock lines, four regional clock lines, and two fast
regional clock lines. Multiplexers are used with these clocks to form eight
bit busses to drive LAB row clocks, column IOE clocks, or row IOE clocks.
Another multiplexer is used at the LAB level to select two of the eight row
clocks to feed the LE registers within the LAB. See
This is a set of two multiplexers.
In addition to the FCLK pin inputs, there is also an input from the I/O interconnect.
(1), (2)
(1), (2)
Figure
FCLK3
FCLK1
2–45:
FCLK0
FCLK2
(1), (2)
(1), (2)
(1), (2)
(1), (2)
FCLK7
FCLK5
FCLK6
FCLK4
(1), (2)
(1), (2)
Figure
Altera Corporation
2–46.
fclk[1..0]
July 2005
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