EP1S40B956C6 Altera, EP1S40B956C6 Datasheet - Page 44
![IC STRATIX FPGA 40K LE 956-BGA](/photos/6/73/67334/544-stratix_956-bga_sml.jpg)
EP1S40B956C6
Manufacturer Part Number
EP1S40B956C6
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S40B956C6
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1423
EP1S40SB956C6
EP1S40SB956C6
Available stocks
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Quantity
Price
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260
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EP1S40B956C6
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ALTERA
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Part Number:
EP1S40B956C6
Manufacturer:
ALTERA/阿尔特拉
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Company:
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ALTERA
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Part Number:
EP1S40B956C6N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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TriMatrix Memory
Figure 2–16. M512 RAM Block LAB Row Interface
2–30
Stratix Device Handbook, Volume 1
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
C4 and C8
Interconnects
8
Small RAM Block Local
Interconnect Region
10
M4K RAM Blocks
The M4K RAM block includes support for true dual-port RAM. The M4K
RAM block is used to implement buffers for a wide variety of applications
such as storing processor code, implementing lookup schemes, and
implementing larger memory applications. Each block contains
4,608 RAM bits (including parity bits). M4K RAM blocks can be
configured in the following modes:
■
■
■
■
■
■
When configured as RAM or ROM, you can use an initialization file to
pre-load the memory contents.
True dual-port RAM
Simple dual-port RAM
Single-port RAM
FIFO
ROM
Shift register
2
datain
Clocks
M512 RAM
LAB Row Clocks
Block
dataout
address
Signals
Control
Altera Corporation
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
R4 and R8
Interconnects
July 2005
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