EP1S40B956C6 Altera, EP1S40B956C6 Datasheet - Page 72
![IC STRATIX FPGA 40K LE 956-BGA](/photos/6/73/67334/544-stratix_956-bga_sml.jpg)
EP1S40B956C6
Manufacturer Part Number
EP1S40B956C6
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S40B956C6
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1423
EP1S40SB956C6
EP1S40SB956C6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S40B956C6
Manufacturer:
ALTERA
Quantity:
260
Company:
Part Number:
EP1S40B956C6
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1S40B956C6
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP1S40B956C6N
Manufacturer:
ALTERA
Quantity:
229
Part Number:
EP1S40B956C6N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Digital Signal Processing Block
2–58
Stratix Device Handbook, Volume 1
Input Registers
A bank of optional input registers is located at the input of each multiplier
and multiplicand inputs to the multiplier. When these registers are
configured for parallel data inputs, they are driven by regular routing
resources. You can use a clock signal, asynchronous clear signal, and a
clock enable signal to independently control each set of A and B inputs for
each multiplier in the DSP block. You select these control signals from a
set of four different clock[3..0], aclr[3..0], and ena[3..0]
signals that drive the entire DSP block.
You can also configure the input registers for a shift register application.
In this case, the input registers feed the multiplier and drive two
dedicated shift output lines: shiftoutA and shiftoutB. The shift
outputs of one multiplier block directly feed the adjacent multiplier block
in the same DSP block (or the next DSP block) as shown in
form a shift register chain. This chain can terminate in any block, that is,
you can create any length of shift register chain up to 224 registers. You
can use the input shift registers for FIR filter applications. One set of shift
inputs can provide data for a filter, and the other are coefficients that are
optionally loaded in serial or parallel. When implementing 9 × 9- and
18 × 18-bit multipliers, you do not need to implement external shift
registers in LAB LEs. You implement all the filter circuitry within the DSP
block and its routing resources, saving LE and general routing resources
for general logic. External registers are needed for shift register inputs
when using 36 × 36-bit multipliers.
Altera Corporation
Figure
July 2005
2–33, to