EP1S40B956C6 Altera, EP1S40B956C6 Datasheet - Page 175
![IC STRATIX FPGA 40K LE 956-BGA](/photos/6/73/67334/544-stratix_956-bga_sml.jpg)
EP1S40B956C6
Manufacturer Part Number
EP1S40B956C6
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S40B956C6
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1423
EP1S40SB956C6
EP1S40SB956C6
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ALTERA
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EP1S40B956C6
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Altera Corporation
January 2006
Figures 4–1
waveforms, respectively, for all differential I/O standards (LVDS, 3.3-V
PCML, LVPECL, and HyperTransport technology).
Figure 4–1. Receiver Input Waveforms for Differential I/O Standards
Single-Ended Waveform
Differential Waveform
Table 4–9. Overshoot Input Voltage with Respect to Duty Cycle (Part 2 of 2)
and
V
Vin (V)
CM
4–2
4.3
4.4
4.5
V
ID
show receiver input and transmitter output
V
ID
Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Maximum Duty Cycle (%)
V
ID
p − n = 0 V
30
17
10
Positive Channel (p) = V
Negative Channel (n) = V
Ground
4–5
IH
IL
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