EP1SGX25DF672I6 Altera, EP1SGX25DF672I6 Datasheet - Page 179

• Manufacturer Part Number: EP1SGX25DF672I6
• Description: IC STRATIX GX FPGA 25K 672-FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX25DF672I6

• Number Of Logic Elements/cells: 25660
• Number Of Labs/clbs: 2566
• Total Ram Bits: 1944576
• Number Of I /o: 455
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 25660
• # I/os (max): 455
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 25660
• Ram Bits: 1944576
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
February 2005
The bus-hold circuitry uses a resistor with a nominal resistance (R
approximately 7 kΩ to weakly pull the signal level to the last-driven state.
The chapter DC & Switching Characteristics of the Stratix GX Device
Handbook, Volume 1 gives the specific sustaining current driven through
this resistor and the overdrive current used to identify the next-driven
input level. This information is provided for each V
The bus-hold circuitry is active only after configuration. When going into
user mode, the bus-hold circuit captures the value on the pin present at
the end of configuration.
Programmable Pull-Up Resistor
Each Stratix GX device I/O pin provides an optional programmable pull-
up resistor during user mode. If this feature is enabled for an I/O pin, the
pull-up resistor (typically 25 kΩ) weakly holds the output to the V
level of the output pin’s bank.
the weak pull-up resistor feature.
Advanced I/O Standard Support
Stratix GX device IOEs support the following I/O standards:
■
■
■
■
■
■
■
■
Note to
(1)
I/O pins
CLK[15..0]
FCLK
FPLL[7..10]CLK
Configuration pins
JTAG pins
Table 4–26. Programmable Weak Pull-Up Resistor Support
LVTTL
LVCMOS
1.5 V
1.8 V
2.5 V
3.3-V PCI
3.3-V PCI-X 1.0
3.3-V AGP (1
TDO pins do not support programmable weak pull-up resistors.
Table
4–26:
Pin Type
×
and 2
×
)
Table 4–26
Stratix GX Device Handbook, Volume 1
Programmable Weak Pull-Up Resistor
shows which pin types support
Stratix GX Architecture
CCIO
v
v
v
(1)
voltage level.
BH
CCIO
4–113
) of