EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 3

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Table 1–1. Features in Arria II Devices
Total Transceivers
ALMs
LEs
PCIe hard IP blocks
M9K Blocks
M144K Blocks
Total Embedded Memory in M9K
Blocks (Kbits)
Total On-Chip Memory
(M9K +M144K + MLABs) (Kbits)
Embedded Multipliers (18 × 18)
General Purpose PLLs
Transceiver TX PLLs (3),
User I/O Banks (5),
High-Speed LVDS SERDES
(up to 1.25 Gbps)
Notes to
(1) The total number of transceivers is divided equally between the left and right side of each device, except for the devices in the F780 package. These devices have eight transceiver channels located only on
(2) This is in four multiplier adder mode.
(3) The FPGA fabric can use these phase locked-loops (PLLs) if they are not used by the transceiver.
(4) The number of PLLs depends on the package. Transceiver transmitter (TX) PLL count = (number of transceiver blocks)
(5) Banks 3C and 8C are dedicated configuration banks and do not have user I/O pins.
(6) For Arria II GZ devices, the user I/Os count from pin-out files includes all general purpose I/O, dedicated clock pins, and dual purpose configuration pins. Transceiver pins and dedicated configuration pins
(7) For Arria II GZ devices, total pairs of high-speed LVDS SERDES take the lowest channel count of RX/TX.For more information, refer to the
(8) The smallest pin package (780-pin package) does not support high-speed LVDS SERDES.
the right side of the device.
are not included in the pin count.
Table
1–1:
Feature
(7)
(1)
(6)
Table 1–1
(4)
(2)
lists the Arria II device features.
8, 24, or 28 8, 24, or 28 24, 28, or 32
EP2AGX45
18,050
42,959
2,871
3,435
2 or 4
319
232
—
8
1
4
6
EP2AGX65
25,300
60,214
2 or 4
4,455
5,246
495
312
—
8
1
4
6
EP2AGX95
37,470
89,178
4 or 6
5,508
6,679
612
448
12
—
Arria II GX Devices
1
6
8
EP2AGX125
24, 28, 32
118,143
49,640
6,570
8,121
4 or 6
730
576
12
—
1
6
8
EP2AGX190
28 or 48
181,165
76,120
7,560
9,939
6 or 8
840
656
16
—
12
1
6
×
2.
EP2AGX260
24 or 48
102,600
244,188
11,756
8,550
6 or 8
950
736
16
—
12
1
6
High-Speed I/O Interfaces and DPA in Arria II Devices
EP2AGZ225
16 or 24
224,000
16 or 20
42 or 86
8 or 12
89,600
11,115
13,915
1,235
6 or 8
800
—
1
Arria II GZ Devices
0 (8), 42, or 86 0 (8), 42, or 86
EP2AGZ300
8, 16, or 20
4, 6, or 8
16 or 24
119,200
298,000
8 or 12
14,688
18,413
1,248
920
24
1
EP2AGZ350
8, 16, or 20
4, 6, or 8
16 or 24
139,400
348,500
8 or 12
16,416
20,772
1,248
1,040
chapter.
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