EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet
EP2AGX65DF29I5N
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EP2AGX65DF29I5N Summary of contents
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
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... Emulated LVDS output support with a data rate 1152 Mbps Arria II Device Handbook Volume 1: Device Interfaces and Integration Chapter 1: Overview for the Arria II Device Family ® (SRIO), Common Public Radio Interface (CPRI), OBSAI, ) and on-chip parallel (R S Arria II Device Feature ) termination with auto-calibration T ) termination for differential D December 2010 Altera Corporation ...
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Table 1–1 lists the Arria II device features. Table 1–1. Features in Arria II Devices Feature EP2AGX45 Total Transceivers (1) 8 ALMs 18,050 LEs 42,959 PCIe hard IP blocks 1 M9K Blocks 319 M144K Blocks — Total Embedded Memory in ...
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... TX, or eTX) eTX) 105(R D 85(R or eTX) D eTX) + +84(RX,TX 452 104(RX, TX, or eTX) eTX) 145(R D 85(R or eTX) D eTX) + +84(RX, TX 612 144(RX, TX, or eTX) eTX) 85(R , eTX) 145(R , eTX +84(RX, TX 612 144(RX, TX, or eTX) eTX) December 2010 Altera Corporation (8) — — ...
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... EP2AGX95 — EP2AGX125 — EP2AGX190 — EP2AGX260 — EP2AGZ225 — EP2AGZ300 — EP2AGZ350 — December 2010 Altera Corporation (Note 1152-Pin Flip Chip FBGA 35 mm × I/O LVDS (7) 135 (RX or eTX) + — 554 140 (TX or eTX) 135 (RX or eTX 554 140 (TX or eTX) ...
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... Arria II Device Architecture IV device family with a PLL Memory Interface High-Speed Differential I/O with DPA, General Purpose I/O, and Memory Interface PLL PLL High-Speed Differential I/O with DPA, General Purpose I/O, and Memory Interface PLL DLL Memory Interface December 2010 Altera Corporation ...
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... On-die power supply regulators for transmitter and receiver PLL charge pump ■ and voltage-controlled oscillator (VCO) for superior noise immunity Calibration circuitry for transmitter and receiver on-chip termination (OCT) ■ resistors December 2010 Altera Corporation General Purpose General Purpose PLL PLL I/O and Memory I/O and Memory ...
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... Arria II Device Handbook Volume 1: Device Interfaces and Integration Feature Descriptions Hard IP Data Link Layer and Transaction Layer Hard IP Data Link Layer and custom Soft IP Transaction Layer Transceiver Architecture in Arria II Devices Chapter 1: Overview for the Arria II Device Family Arria II Device Architecture chapter. December 2010 Altera Corporation ...
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... The Quartus M144K memory blocks by instantiating memory using a dedicated megafunction wizard or by inferring memory directly from VHDL or Verilog source code. December 2010 Altera Corporation ® II software allows you to take advantage of MLABs, M9K, and Arria II Device Handbook Volume 1: Device Interfaces and Integration 1– ...
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... Table 1–7. I/O Standard LVTTL, LVCMOS, SSTL, HSTL, PCIe, and PCI-X SSTL, HSTL, LVPECL, LVDS, mini-LVDS, Bus LVDS (BLVDS) (1), and RSDS 1–8. Arria II Device Architecture December 2010 Altera Corporation ...
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... MHz to support both low-cost and high-end clock performance ■ FPGA fabric can use the unused transceiver PLLs to provide more flexibility December 2010 Altera Corporation i/O Bank Bank 3C, Bank 7B, and Bank 8C Bank 3A, Bank 4A, Bank 7A, and Bank 8A ...
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... External Memory Interfaces in Arria II Devices Nios II Arria II devices support all variants of the NIOS ■ Nios II processors are supported by an array of software tools from Altera and ■ leading embedded partners and are used by more designers than any other configurable processor Configuration Features ■ ...
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... Boundary-scan test (BST) architecture offers the capability to test pin connections ■ without using physical test probes and capture functional data while a device is operating normally December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration 1–13 ...
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... Optional Suffix Indicates specific device options ES: Engineering sample N: Lead-free devices Speed Grade with 3 being the fastest Operating Temperature C: Commercial temperature (t = 0°C to 85° Industrial temperature (t = -40°C to 100°C) J 1–6, Table 1–7, and Table 1–9 section December 2010 Altera Corporation ...