EPF10K50EQI240-2 Altera, EPF10K50EQI240-2 Datasheet - Page 58
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EPF10K50EQI240-2
Manufacturer Part Number
EPF10K50EQI240-2
Description
IC FLEX 10KE FPGA 50K 240-PQFP
Manufacturer
Altera
Series
FLEX-10KE®r
Datasheet
1.EPF10K30ETC144-3.pdf
(100 pages)
Specifications of EPF10K50EQI240-2
Number Of Logic Elements/cells
2880
Number Of Labs/clbs
360
Total Ram Bits
40960
Number Of I /o
189
Number Of Gates
199000
Voltage - Supply
2.3 V ~ 2.7 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
240-MQFP, 240-PQFP
Family Name
FLEX 10KE
Number Of Usable Gates
50000
Number Of Logic Blocks/elements
2880
# Registers
189
# I/os (max)
189
Frequency (max)
200MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
2.5V
Logic Cells
2880
Ram Bits
40960
Device System Gates
199000
Operating Supply Voltage (min)
2.3V
Operating Supply Voltage (max)
2.7V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
240
Package Type
PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1945
EPF10K50EQI240-2
EPF10K50EQI240-2
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF10K50EQI240-2
Manufacturer:
NEC
Quantity:
10
Company:
Part Number:
EPF10K50EQI240-2N
Manufacturer:
ALTERA22
Quantity:
209
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
58
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t
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t
t
t
t
t
t
EABDATA1
EABDATA2
EABWE1
EABWE2
EABRE1
EABRE2
EABCLK
EABCO
EABBYPASS
EABSU
EABH
EABCLR
AA
WP
RP
WDSU
WDH
WASU
WAH
RASU
RAH
WO
DD
EABOUT
EABCH
EABCL
Table 26. EAB Timing Microparameters
Symbol
Data or address delay to EAB for combinatorial input
Data or address delay to EAB for registered input
Write enable delay to EAB for combinatorial input
Write enable delay to EAB for registered input
Read enable delay to EAB for combinatorial input
Read enable delay to EAB for registered input
EAB register clock delay
EAB register clock-to-output delay
Bypass register delay
EAB register setup time before clock
EAB register hold time after clock
EAB register asynchronous clear time to output delay
Address access delay (including the read enable to output delay)
Write pulse width
Read pulse width
Data setup time before falling edge of write pulse
Data hold time after falling edge of write pulse
Address setup time before rising edge of write pulse
Address hold time after falling edge of write pulse
Address setup time with respect to the falling edge of the read enable
Address hold time with respect to the falling edge of the read enable
Write enable to data output valid delay
Data-in to data-out valid delay
Data-out delay
Clock high time
Clock low time
Note (1)
Parameter
Altera Corporation
(5)
(5)
(5)
(5)
Conditions