EPF10K50EQI240-2 Altera, EPF10K50EQI240-2 Datasheet - Page 56
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EPF10K50EQI240-2
Manufacturer Part Number
EPF10K50EQI240-2
Description
IC FLEX 10KE FPGA 50K 240-PQFP
Manufacturer
Altera
Series
FLEX-10KE®r
Datasheet
1.EPF10K30ETC144-3.pdf
(100 pages)
Specifications of EPF10K50EQI240-2
Number Of Logic Elements/cells
2880
Number Of Labs/clbs
360
Total Ram Bits
40960
Number Of I /o
189
Number Of Gates
199000
Voltage - Supply
2.3 V ~ 2.7 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
240-MQFP, 240-PQFP
Family Name
FLEX 10KE
Number Of Usable Gates
50000
Number Of Logic Blocks/elements
2880
# Registers
189
# I/os (max)
189
Frequency (max)
200MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
2.5V
Logic Cells
2880
Ram Bits
40960
Device System Gates
199000
Operating Supply Voltage (min)
2.3V
Operating Supply Voltage (max)
2.7V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
240
Package Type
PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1945
EPF10K50EQI240-2
EPF10K50EQI240-2
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF10K50EQI240-2
Manufacturer:
NEC
Quantity:
10
Company:
Part Number:
EPF10K50EQI240-2N
Manufacturer:
ALTERA22
Quantity:
209
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
56
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
LUT
CLUT
RLUT
PACKED
EN
CICO
CGEN
CGENR
CASC
C
CO
COMB
SU
H
PRE
Table 24. LE Timing Microparameters (Part 1 of 2)
Symbol
LUT delay for data-in
LUT delay for carry-in
LUT delay for LE register feedback
Data-in to packed register delay
LE register enable delay
Carry-in to carry-out delay
Data-in to carry-out delay
LE register feedback to carry-out delay
Cascade-in to cascade-out delay
LE register control signal delay
LE register clock-to-output delay
Combinatorial delay
LE register setup time for data and enable signals before clock; LE register
recovery time after asynchronous clear, preset, or load
LE register hold time for data and enable signals after clock
LE register preset delay
Figure 28. Synchronous Bidirectional Pin External Timing Model
Tables 24
parameters.
parameters and their symbols.
Dedicated
Clock
through
Tables 29
Parameter
28
describe the FLEX 10KE device internal timing
through
Note (1)
Output Register
30
Input Register
OE Register
D
D
D
describe the FLEX 10KE external timing
CLRN
CLRN
CLRN
PRN
PRN
PRN
Q
Q
Q
t
OUTCOBIDIR
t
t
XZBIDIR
ZXBIDIR
Altera Corporation
t
t
INHBIDIR
INSUBIDIR
Bidirectional
Pin
Condition