EP3C40F324I7N Altera, EP3C40F324I7N Datasheet - Page 82
![IC CYCLONE III FPGA 40K 324 FBGA](/photos/6/70/67067/544-324-fbga_sml.jpg)
EP3C40F324I7N
Manufacturer Part Number
EP3C40F324I7N
Description
IC CYCLONE III FPGA 40K 324 FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C40F324I7N.pdf
(274 pages)
Specifications of EP3C40F324I7N
Number Of Logic Elements/cells
39600
Number Of Labs/clbs
2475
Total Ram Bits
1161216
Number Of I /o
195
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
324-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
39600
# I/os (max)
195
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
39600
Ram Bits
1161216
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Package Type
FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2547
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C40F324I7N
Manufacturer:
ALTERA31
Quantity:
129
Part Number:
EP3C40F324I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
5–18
Clock Switchover
Cyclone III Device Handbook, Volume 1
f
If you use the SignalTap
locked signal goes low only when areset is deasserted. If the areset signal is not
enabled, the extra logic is not implemented in the ALTPLL megafunction.
For more information about the PLL control signals, refer to the
User
The clock switchover feature allows the PLL to switch between two reference input
clocks. Use this feature for clock redundancy or for a dual-clock domain application,
such as a system that turns on the redundant clock if the previous clock stops
running. Your design can automatically perform clock switchover when the clock is
no longer toggling, or based on the user control signal, clkswitch.
Automatic Clock Switchover
Cyclone III device family PLLs support a fully configurable clock switchover
capability.
When the current reference clock is not present, the clock-sense block automatically
switches to the backup clock for PLL reference. The clock switchover circuit also
sends out three status signals—clkbad[0], clkbad[1], and activeclock—from
the PLL to implement a custom switchover circuit. You can select a clock source at the
backup clock by connecting it to the inclk1 port of the PLL in your design.
Figure 5–14
Figure 5–14. Automatic Clock Switchover Circuit
Guide.
inclk1
inclk0
shows the block diagram of the switchover circuit built into the PLL.
muxout
®
II tool to probe the locked signal before the D flip-flop, the
clksw
n Counter
Sense
Clock
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
refclk
Switchover
Machine
State
© December 2009 Altera Corporation
PFD
ALTPLL Megafunction
clkswitch
(provides manual
switchover support)
fbclk
clkbad0
clkbad1
Activeclock
Hardware Features