EP3C40F324I7N Altera, EP3C40F324I7N Datasheet - Page 197
![IC CYCLONE III FPGA 40K 324 FBGA](/photos/6/70/67067/544-324-fbga_sml.jpg)
EP3C40F324I7N
Manufacturer Part Number
EP3C40F324I7N
Description
IC CYCLONE III FPGA 40K 324 FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C40F324I7N.pdf
(274 pages)
Specifications of EP3C40F324I7N
Number Of Logic Elements/cells
39600
Number Of Labs/clbs
2475
Total Ram Bits
1161216
Number Of I /o
195
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
324-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
39600
# I/os (max)
195
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
39600
Ram Bits
1161216
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Package Type
FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2547
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C40F324I7N
Manufacturer:
ALTERA31
Quantity:
129
Part Number:
EP3C40F324I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
© December 2009
Altera Corporation
In a multi-device PS configuration, the nCE pin of the first device is connected to GND
while its nCEO pin is connected to the nCE pin of the next device in the chain. The nCE
input of the last device comes from the previous device, while its nCEO pin is left
floating. After the first device completes configuration in a multi-device configuration
chain, its nCEO pin drives low to activate the nCE pin of the second device, which
prompts the second device to begin configuration. The second device in the chain
begins configuration in one clock cycle. Therefore, the transfer of data destinations is
transparent to the external host device. All other configuration pins (nCONFIG,
nSTATUS, DCLK, DATA[0], and CONF_DONE) are connected to every device in the
chain. Configuration signals can require buffering to ensure signal integrity and
prevent clock skew problems. Ensure that the DCLK and DATA lines are buffered.
Because all device CONF_DONE pins are tied together, all devices initialize and enter
user mode at the same time.
If any device detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured because all nSTATUS and CONF_DONE pins are tied
together. For example, if the first device flags an error on nSTATUS, it resets the chain
by pulling its nSTATUS pin low. This behavior is similar to a single device detecting
an error.
You can have multiple devices that contain the same configuration data in your
system. To support this configuration scheme, all device nCE inputs are tied to GND,
while the nCEO pins are left floating. All other configuration pins (nCONFIG,
nSTATUS, DCLK, DATA[0], and CONF_DONE) are connected to every device in the
chain. Configuration signals can require buffering to ensure signal integrity and
prevent clock skew problems. Ensure that the DCLK and DATA lines are buffered.
Devices must be of the same density and package. All devices start and complete
configuration at the same time.
Cyclone III Device Handbook, Volume 1
9–37