EP3C40F324I7N Altera, EP3C40F324I7N Datasheet - Page 263
![IC CYCLONE III FPGA 40K 324 FBGA](/photos/6/70/67067/544-324-fbga_sml.jpg)
EP3C40F324I7N
Manufacturer Part Number
EP3C40F324I7N
Description
IC CYCLONE III FPGA 40K 324 FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C40F324I7N.pdf
(274 pages)
Specifications of EP3C40F324I7N
Number Of Logic Elements/cells
39600
Number Of Labs/clbs
2475
Total Ram Bits
1161216
Number Of I /o
195
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
324-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
39600
# I/os (max)
195
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
39600
Ram Bits
1161216
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Package Type
FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2547
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C40F324I7N
Manufacturer:
ALTERA31
Quantity:
129
Part Number:
EP3C40F324I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 11: SEU Mitigation in the Cyclone III Device Family
Software Support
Table 11–8. CRC Block Input and Output Ports (Part 1 of 2)
© December 2009
<crcblock_name>
.clk(<clock
source>
.shiftnld
(<shiftnld
source>)
Port
1
Altera Corporation
Table 11–7
Table 11–7. WYSIWYG Atoms
To enable the cycloneiii_crcblock primitive in version 8.0 SP1 or earlier of the
Quartus II software, turn on the error detection CRC feature in the Device and Pins
Options dialog box. This is not required when you are using version 8.1 and later of
the Quartus II software.
Example 11–1
WYSIWYG atom in a Cyclone III LS device.
Example 11–1. Error Detection Block Diagram
cycloneiiils_crcblock<crcblock_name>
(
.clk(<clock source>),
.shiftnld(<shiftnld source>),
.ldsrc(<ldsrc source>),
.crcerror(<crcerror out destination>),
.regout(<output destination>),
.cyclecomplete(<cyclecomplete destination>),
);
Table 11–8
input and output ports of the atoms for Cyclone III device family are similar, except
for the cyclecomplete port which is for Cyclone III LS devices only.
Cyclone III
Cyclone III LS
Input/Output
Input
Input
Input
lists the name of the WYSIWYG atom for Cyclone III device family.
lists the input and output ports that must be included in the atom. The
Device
shows an example of how to define the input and output ports of a
Unique identifier for the CRC block, and represents any identifier name that is
legal for the given description language (For example Verilog HDL, VHDL,
AHDL). This field is required.
This signal designates the clock input of this cell. All operations of this cell are
with respect to the rising edge of the clock. Whether it is the loading of the
data into the cell or data out of the cell, it always occurs on the rising edge.
This port is required.
This signal is an input into the error detection block. If shiftnld=1, the
data is shifted from the internal shift register to the regout at each rising
edge of clk. If shiftnld=0, the shift register parallel loads either the
pre-calculated CRC value or the update register contents depending on the
ldsrc port input. This port is required.
cycloneiiils_crcblock
Definition
cycloneiii_crcblock
WYSIWYG Atom
Cyclone III Device Handbook, Volume 1
11–9