EP3C40F324I7N Altera, EP3C40F324I7N Datasheet - Page 224
![IC CYCLONE III FPGA 40K 324 FBGA](/photos/6/70/67067/544-324-fbga_sml.jpg)
EP3C40F324I7N
Manufacturer Part Number
EP3C40F324I7N
Description
IC CYCLONE III FPGA 40K 324 FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C40F324I7N.pdf
(274 pages)
Specifications of EP3C40F324I7N
Number Of Logic Elements/cells
39600
Number Of Labs/clbs
2475
Total Ram Bits
1161216
Number Of I /o
195
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
324-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
39600
# I/os (max)
195
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
39600
Ram Bits
1161216
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Package Type
FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2547
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C40F324I7N
Manufacturer:
ALTERA31
Quantity:
129
Part Number:
EP3C40F324I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
9–64
Table 9–20. JTAG Programming Instruction Flows
Cyclone III Device Handbook, Volume 1
FACTORY
ACTIVE_DISENGAGE
CONFIG_IO
Other JTAG instructions
JTAG_PROGRAM
CHECK_STATUS
JTAG_STARTUP
JTAG TAP Reset/ other instruction
Notes to
(1) “R” indicates that the instruction is required to be executed before the next instruction, “O” indicates the optional instruction, “Rc” indicates
(2) AP configuration is for Cyclone III devices only.
the recommended instruction, and “NA” indicates that the instruction is not allowed to be executed in this mode.
Table
JTAG Instruction
9–20:
ACTIVE_DISENGAGE
The ACTIVE_DISENGAGE instruction places the active configuration controller (AS
and AP) into an idle state prior to JTAG programming. The active configuration
controller is the AS controller when the MSEL pins are set to AS configuration scheme
and the AP controller when the MSEL pins are set to the AP configuration scheme.
The two purposes of placing the active controllers in an idle state are:
■
■
The ACTIVE_DISENGAGE instruction is required before JTAG programming
regardless of the current state of the Cyclone III device family if the MSEL pins are set
to an active configuration scheme (AS or AP). If the ACTIVE_DISENGAGE instruction
is issued during a passive configuration scheme (PS or FPP), it has no effect on the
Cyclone III device family. Similarly, the CONFIG_IO instruction is issued after an
ACTIVE_DISENGAGE instruction, but is no longer required to properly halt
configuration.
for each configuration mode. The ordering of the required instructions is a hard
requirement and must be met to ensure functionality.
In AS or AP configuration schemes, the ACTIVE_DISENGAGE instruction puts the
active configuration controllers into idle state. If a successful JTAG programming is
executed, the active controllers are automatically re-engaged after user mode is
reached using JTAG programming. This causes the active controllers to transition to
their respective user mode states.
To ensure that they are not trying to configure the device in their respective
configuration modes during JTAG programming
To allow the controllers to properly recognize a successful JTAG programming
that results in the device reaching user mode
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Table 9–20
NA
PS
Rc
Rc
O
O
R
R
R
Prior to User Mode
Configuration Scheme and Current State of the Cyclone III Device
Configuration)
(Interrupting
FPP
(Note 1)
NA
Rc
Rc
lists the required, recommended, and optional instructions
O
O
R
R
R
NA
AS
Rc
R
O
O
R
R
R
(2)
NA
AP
Rc
R
O
O
R
R
R
NA
PS
Rc
O
O
O
R
R
R
User Mode
FPP
NA
Rc
O
O
O
R
R
R
NA
AS
Rc
O
O
O
R
R
R
© December 2009 Altera Corporation
(2)
NA
AP
Rc
R
O
O
R
R
R
NA
PS
Rc
R
O
O
R
R
R
Configuration Features
FPP
Power Up
NA
Rc
R
O
O
R
R
R
NA
AS
Rc
R
R
O
R
R
R
AP(
NA
NA
Rc
2)
R
O
R
R
R