EP2SGX60EF1152C5N Altera, EP2SGX60EF1152C5N Datasheet - Page 173

• Manufacturer Part Number: EP2SGX60EF1152C5N
• Description: IC STRATIX II GX 60K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX60EF1152C5N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 534
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 534
• Frequency (max): 609.76MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2185

Altera Corporation
June 2009
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
Note to
(1)
T
V
V
V
V
V
V
V
Table 4–3. Stratix II GX Device Recommended Operating Conditions (Part 2 of 2)
Table 4–4. Stratix II GX Transceiver Block Absolute Maximum Ratings
Symbol
J
CCA
CCP
CCR
CCT
CCT_B
CCL
CCH_B
Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply.
During transitions, the inputs may overshoot to the voltage shown in
The DC case is equivalent to 100% duty cycle. During transitions, the inputs may undershoot to –2.0 V for input
currents less than 100 mA and periods shorter than 20 ns.
Maximum V
V
time, the Stratix II GX device will not configure successfully. If the system does not allow for a V
of 100 ms or less, hold nCONFIG low until all power supplies are reliable.
All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before V
are powered.
V
The device can tolerate prolonged operation at this absolute maximum, as long as the maximum specification is
not violated.
Symbol
CCPD
CCIO
Table
Table
maximum and minimum conditions for PCI and PCI-X are shown in parentheses.
must ramp-up from 0 V to 3.3 V within 100 μs to 100 ms. If V
Operating junction temperature
4–4:
4–3:
CC
rise time is 100 ms, and V
Transceiver block supply
voltage
Transceiver block supply
voltage
Transceiver block supply
Voltage
Transceiver block supply
voltage
Transceiver block supply
voltage
Transceiver block supply
voltage
Transceiver block supply
voltage
Parameter
Parameter
Transceiver Block Characteristics
Tables 4–4
through
CC
For commercial use
For industrial use
must rise monotonically from ground to V
Commercial and
industrial
Commercial and
industrial
Commercial and
industrial
Commercial and
industrial
Commercial and
industrial
Commercial and
industrial
Commercial and
industrial
4–6
Conditions
Conditions
contain transceiver block specifications.
Stratix II GX Device Handbook, Volume 1
CCPD
Table 4–2
is not ramped up within this specified
DC and Switching Characteristics
Minimum Maximum
Note (1)
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
based upon the input duty cycle.
Minimum
–40
0
CC
CCINT
.
Note (1)
4.6
1.8
1.8
1.8
1.8
1.8
2.4
, V
CCPD
Maximum Unit
CCPD
100
85
ramp-up time
, and V
Units
V
V
V
V
V
V
V
CCIO
C
C
4–3