EP2SGX60EF1152C5N Altera, EP2SGX60EF1152C5N Datasheet - Page 122

• Manufacturer Part Number: EP2SGX60EF1152C5N
• Description: IC STRATIX II GX 60K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX60EF1152C5N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 534
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 534
• Frequency (max): 609.76MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2185

I/O Structure
Figure 2–78. Column I/O Block Connection to the Interconnect
Note to
(1)
2–114
Stratix II GX Device Handbook, Volume 1
The 32 data and control signals consist of eight data out lines: four lines each for DDR applications
io_dataouta[3..0] and io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables
io_ce_in[3..0], four output clock enables io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous
clear and preset signals io_aclr/apreset[3..0], and four synchronous clear and preset signals
io_sclr/spreset[3..0]
Figure
Local Interconnect
from Logic Array (1)
Interconnects
R4 & R24
Control Signals
2–78:
I/O Block
32 Data &
Interconnect
LAB
LAB Local
Figure 2–78
.
shows how a column I/O block connects to the logic array.
Vertical I/O Block
Interconnects
C4 & C16
32
LAB
IO_dataina[3..0]
IO_datainb[3..0]
LAB
Vertical I/O
Block Contains
up to Four IOEs
io_clk[7..0]
Altera Corporation
October 2007