EP2SGX60EF1152C5N Altera, EP2SGX60EF1152C5N Datasheet - Page 147
EP2SGX60EF1152C5N
Manufacturer Part Number
EP2SGX60EF1152C5N
Description
IC STRATIX II GX 60K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX60EF1152C5N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
534
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
60440
# I/os (max)
534
Frequency (max)
609.76MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2185
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2SGX60EF1152C5N
Manufacturer:
ALTERA
Quantity:
533
Part Number:
EP2SGX60EF1152C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Figure 2–88. Stratix II GX Transmitter Channel
Altera Corporation
October 2007
refclk
Fast
PLL
Each Stratix II GX receiver channel features a DPA block for phase
detection and selection, a SERDES, a synchronizer, and a data realigner
circuit. You can bypass the dynamic phase aligner without affecting the
basic source-synchronous operation of the channel. In addition, you can
dynamically switch between using the DPA block or bypassing the block
via a control signal from the logic array.
Data from R4, R24, C4, or
direct link interconnect
Interconnect
Local
diffioclk
load_en
10
10
Stratix II GX Device Handbook, Volume 1
Dedicated
Transmitter
Interface
+
–
Stratix II GX Architecture
Regional or
global clock
Up to 1 Gbps
2–139
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