AT40K20-2EQC Atmel, AT40K20-2EQC Datasheet - Page 35

• Manufacturer Part Number: AT40K20-2EQC
• Description: IC FPGA 20K GATES 240PQFP
• Manufacturer: Atmel
• Series: AT40K/KLVr

Specifications of AT40K20-2EQC

• Number Of Logic Elements/cells: 1024
• Total Ram Bits: 8192
• Number Of I /o: 193
• Number Of Gates: 30000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 240-BFQFP
• Family Name: AT40K
• Number Of Usable Gates: 30000
• Number Of Logic Blocks/elements: 1024
• # Registers: 1024
• # I/os (max): 193
• Process Technology: 0.6um (CMOS)
• Operating Supply Voltage (typ): 5V
• Logic Cells: 1024
• Ram Bits: 8192
• Device System Gates: 30000
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Labs/clbs: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: AT40K202EQC

AC Timing Characteristics – 3.3V Operation AT40KLV
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: V
Minimum times based on best case: V
Maximum delays are the average of t
Clocks and Reset Input buffers are measured from a V
Maximum times for clock input buffers and internal drivers are measured for rising edge delays only.
0896C–FPGA–04/02
Cell Function
Global Clocks and Set/Reset
GCK Input Buffer
FCK Input Buffer
Clock Column Driver
Clock Sector Driver
GSRN Input Buffer
Global Clock to Output
Fast Clock to Output
Parameter
t
(Maximum)
t
(Maximum)
t
(Maximum)
t
(Maximum)
t
(Maximum)
t
(Maximum)
t
(Maximum)
PD
PD
PD
PD
PD
PD
PD
PDLH
CC
CC
= 3.6V, temperature = 0°C
and t
= 3.0V, temperature = 70°C
Path
pad -> clock
pad -> clock
pad -> clock
pad -> clock
pad -> clock
pad -> clock
pad -> clock
pad -> clock
clock -> colclk
clock -> colclk
clock -> colclk
clock -> colclk
colclk -> secclk
colclk -> secclk
colclk -> secclk
colclk -> secclk
pad -> GSRN
pad -> GSRN
pad -> GSRN
pad -> GSRN
clock pad -> out
clock pad -> out
clock pad -> out
clock pad -> out
clock pad -> out
clock pad -> out
clock pad -> out
clock pad -> out
PDHL
.
IH
of 1.5V at the input pad to the internal V
AT40K/AT40KLV Series FPGA
Device
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
13.0
13.4
13.8
14.5
12.4
12.7
13.0
13.5
1.3
1.5
1.6
1.9
0.7
0.8
0.8
0.9
1.5
1.8
2.0
2.5
1.0
1.0
1.0
1.0
4.5
5.4
6.3
8.2
-3
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Rising edge clock
Rising edge clock
Rising edge clock
Rising edge clock
Rising edge clock
Fully loaded clock tree
Rising edge DFF
20 mA output buffer
50 pf pin load
Rising edge clock
Fully loaded clock tree
Rising edge DFF
20 mA output buffer
50 pf pin load
IH
of 50% of V
CC
.
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