EP2C20F484C8N Altera, EP2C20F484C8N Datasheet - Page 88

• Manufacturer Part Number: EP2C20F484C8N
• Description: IC CYCLONE II FPGA 20K 484-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C20F484C8N

• Number Of Logic Elements/cells: 18752
• Number Of Labs/clbs: 1172
• Total Ram Bits: 239616
• Number Of I /o: 315
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone® II
• Number Of Logic Blocks/elements: 18752
• # I/os (max): 315
• Frequency (max): 402.58MHz
• Process Technology: 90nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 18752
• Ram Bits: 239616
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 1172
• Family Type: Cyclone II
• No. Of I/o's: 315
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 320MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: P0528 - BOARD DEV DE1 ALTERA544-1736 - CYCLONE II STARTER KIT EP2C20N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1668

Power-On Reset Circuitry
4–6
Cyclone II Device Handbook, Volume 1
For Cyclone II devices, wake-up time consists of power-up, POR,
configuration, and initialization. The device must properly go through all
four stages to configure correctly and begin operation. You can calculate
wake-up time using the following equation:
Figure 4–3
Figure 4–3. Cyclone II Wake-Up Time
Note to
(1)
The V
characteristics and the power supply used in your system. The fast-on
devices require a maximum V
POR time of 12 ms.
Configuration time will depend on the configuration mode chosen and
the configuration file size. You can calculate configuration time by
multiplying the number of bits in the configuration file with the period of
the configuration clock. For fast configuration times, you should use
Passive Serial (PS) configuration mode with maximum DCLK frequency
of 100 MHz. In addition, you can use compression to reduce the
configuration file size and speed up the configuration time. The t
or t
1
Wake-Up Time = V
V
CC
Minimum
CD2UMC
V
CC
CC
Figure
ramp must be monotonic.
ramp time and POR time will depend on the device
For more information on the t
to the Configuring Cyclone II Devices chapter in the Cyclone II
Device Handbook.
illustrates the components of wake up time.
parameters will determine the initialization time.
Voltage
V
CC
Time
4–3:
Ramp
CC
Ramp Time + POR Time + Configuration Time + Initialization Time
POR Time
CC
ramp time of 2 ms and have a maximum
Configuration Time
CD2UM
or t
CD2UMC
Altera Corporation
parameters, refer
Initialization
Time
February 2007
CD2UM
Mode
User
Time