EP2C20F484C8N Altera, EP2C20F484C8N Datasheet - Page 162

• Manufacturer Part Number: EP2C20F484C8N
• Description: IC CYCLONE II FPGA 20K 484-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C20F484C8N

• Number Of Logic Elements/cells: 18752
• Number Of Labs/clbs: 1172
• Total Ram Bits: 239616
• Number Of I /o: 315
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone® II
• Number Of Logic Blocks/elements: 18752
• # I/os (max): 315
• Frequency (max): 402.58MHz
• Process Technology: 90nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 18752
• Ram Bits: 239616
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 1172
• Family Type: Cyclone II
• No. Of I/o's: 315
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 320MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: P0528 - BOARD DEV DE1 ALTERA544-1736 - CYCLONE II STARTER KIT EP2C20N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1668

Duty Cycle Distortion
5–72
Cyclone II Device Handbook, Volume 1
For DDIO outputs, you can calculate actual half period from the
following equation:
For example, if the DDR output I/O standard is SSTL-2 Class II, the
maximum DCD for a –5 device is 155 ps (refer to
frequency is 167 MHz, the half-clock period T/2 is:
Notes to
(1)
(2)
1.5-V
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
HSTL-18 Class I
HSTL-15 Class I
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
Differential HSTL-18 Class I
Differential HSTL-15 Class I
LVDS
Simple RSDS
Mini LVDS
PCI
PCI-X
Table 5–57. Maximum for DDIO Output on Row Pins with PLL in the Clock
Path
Row Pins with PLL in the Clock Path
Actual half period = ideal half period – maximum DCD
T/2 = 1/(2* f )= 1 /(2*167 MHz) = 3 ns = 3000 ps
The DCD specification is characterized using the maximum drive strength
available for each I/O standard.
Numbers are applicable for commercial, industrial, and automotive devices.
Notes
Table
(1),
5–57:
(2)
(Part 2 of 2)
280
150
155
180
180
205
150
155
180
180
205
100
285
285
C6
95
95
280
190
200
240
235
220
190
200
240
235
220
110
155
110
305
305
Table
C7
Altera Corporation
5–57). If the clock
280
230
230
260
235
220
230
230
260
235
220
120
155
120
335
335
C8
February 2008
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps