EP2C20F484C8N Altera, EP2C20F484C8N Datasheet - Page 29

IC CYCLONE II FPGA 20K 484-FBGA

EP2C20F484C8N

Manufacturer Part Number
EP2C20F484C8N
Description
IC CYCLONE II FPGA 20K 484-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet

Specifications of EP2C20F484C8N

Number Of Logic Elements/cells
18752
Number Of Labs/clbs
1172
Total Ram Bits
239616
Number Of I /o
315
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone® II
Number Of Logic Blocks/elements
18752
# I/os (max)
315
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
18752
Ram Bits
239616
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
1172
Family Type
Cyclone II
No. Of I/o's
315
I/o Supply Voltage
3.3V
Operating Frequency Max
320MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
P0528 - BOARD DEV DE1 ALTERA544-1736 - CYCLONE II STARTER KIT EP2C20N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1668

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Altera Corporation
February 2007
Each global clock network has a clock control block to select from a
number of input clock sources (PLL clock outputs, CLK[] pins, DPCLK[]
pins, and internal logic) to drive onto the global clock network.
lists how many PLLs, CLK[] pins, DPCLK[] pins, and global clock
networks are available in each Cyclone II device. CLK[] pins are
dedicated clock pins and DPCLK[] pins are dual-purpose clock pins.
Figures 2–11
inputs, DPCLK[] pins, and clock control blocks.
EP2C5
EP2C8
EP2C15
EP2C20
EP2C35
EP2C50
EP2C70
Table 2–2. Cyclone II Device Clock Resources
Device
and
Number of
2–12
PLLs
2
2
4
4
4
4
4
show the location of the Cyclone II PLLs, CLK[]
Number of
CLK Pins
Cyclone II Device Handbook, Volume 1
16
16
16
16
16
8
8
DPCLK Pins
Number of
20
20
20
20
20
Cyclone II Architecture
8
8
Global Clock
Number of
Networks
Table 2–2
16
16
16
16
16
8
8
2–17

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