EP2C20F484C8N Altera, EP2C20F484C8N Datasheet - Page 155

• Manufacturer Part Number: EP2C20F484C8N
• Description: IC CYCLONE II FPGA 20K 484-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C20F484C8N

• Number Of Logic Elements/cells: 18752
• Number Of Labs/clbs: 1172
• Total Ram Bits: 239616
• Number Of I /o: 315
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone® II
• Number Of Logic Blocks/elements: 18752
• # I/os (max): 315
• Frequency (max): 402.58MHz
• Process Technology: 90nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 18752
• Ram Bits: 239616
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 1172
• Family Type: Cyclone II
• No. Of I/o's: 315
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 320MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: P0528 - BOARD DEV DE1 ALTERA544-1736 - CYCLONE II STARTER KIT EP2C20N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1668

Altera Corporation
February 2008
Notes to
(1)
(2)
t
t
t
t
t
t
t
t
t
t
t
t
t
J C P
J C H
J C L
J P S U
J P H
J P C O
J P Z X
J P X Z
J S S U
J S H
J S C O
J S Z X
J S X Z
Table 5–53. Cyclone II JTAG Timing Parameters and Values
Symbol
This information is preliminary.
This specification is shown for 3.3-V LVTTL/LVCMOS and 2.5-V LVTTL/LVCMOS operation of the JTAG pins. For
1.8-V LVTTL/LVCMOS and 1.5-V LVCMOS, the JTAG port and capture register clock setup time is 3 ns and port
clock to output time is 15 ns.
Table
TCK
TCK
TCK
JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
5–53:
f
clock period
clock high time
clock low time
Table 5–53
devices.
1
For more information on JTAG, refer to the
Boundary-Scan Testing for Cyclone II Devices
Handbook.
Parameter
(2)
(2)
Cyclone II devices must be within the first 17 devices in a JTAG
chain. All of these devices have the same JTAG controller. If any
of the Cyclone II devices are in the 18th position or after they will
fail configuration. This does not affect the SignalTap
analyzer.
(2)
shows the JTAG timing parameters and values for Cyclone II
(2)
(2)
DC Characteristics and Timing Specifications
Min
Cyclone II Device Handbook, Volume 1
20
20
10
10
—
—
—
—
—
—
40
5
5
chapter in the Cyclone II
IEEE 1149.1 (JTAG)
Max
13
13
13
25
25
25
—
—
—
—
—
—
—
®
II logic
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5–65