EP2C20F484C8N Altera, EP2C20F484C8N Datasheet - Page 46

• Manufacturer Part Number: EP2C20F484C8N
• Description: IC CYCLONE II FPGA 20K 484-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C20F484C8N

• Number Of Logic Elements/cells: 18752
• Number Of Labs/clbs: 1172
• Total Ram Bits: 239616
• Number Of I /o: 315
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone® II
• Number Of Logic Blocks/elements: 18752
• # I/os (max): 315
• Frequency (max): 402.58MHz
• Process Technology: 90nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 18752
• Ram Bits: 239616
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 1172
• Family Type: Cyclone II
• No. Of I/o's: 315
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 320MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: P0528 - BOARD DEV DE1 ALTERA544-1736 - CYCLONE II STARTER KIT EP2C20N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1668

Embedded Multipliers
Figure 2–18. Multiplier Block Architecture
Note to
(1)
2–34
Cyclone II Device Handbook, Volume 1
If necessary, these signals can be registered once to match the data signal path.
Figure
2–18:
Data A
Data B
Each multiplier operand can be a unique signed or unsigned number.
Two signals, signa and signb, control the representation of each
operand respectively. A logic 1 value on the signa signal indicates that
data A is a signed number while a logic 0 value indicates an unsigned
number.
various operand sign representations. The result of the multiplication is
signed if any one of the operands is a signed value.
Unsigned
Unsigned
Signed
Signed
Table 2–11. Multiplier Sign Representation
Data A (signa Value)
ENA
ENA
D
D
CLRN
CLRN
signa (1)
signb (1)
clock
Q
Q
Table 2–11
ena
aclr
Register
Input
shows the sign of the multiplication result for the
Embedded Multiplier Block
Unsigned
Signed
Unsigned
Signed
Data B (signb Value)
ENA
D
CLRN
Register
Output
Q
Unsigned
Signed
Signed
Signed
Data Out
Altera Corporation
Result
February 2007