EP2C8Q208C8 Altera, EP2C8Q208C8 Datasheet - Page 38

• Manufacturer Part Number: EP2C8Q208C8
• Description: IC CYCLONE II FPGA 8K 208-PQFP
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C8Q208C8

• Number Of Logic Elements/cells: 8256
• Number Of Labs/clbs: 516
• Total Ram Bits: 165888
• Number Of I /o: 138
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Other names: 544-1456

Global Clock Network & Phase-Locked Loops
2–26
Cyclone II Device Handbook, Volume 1
Clock multiplication and division
Phase shift
Programmable duty cycle
Number of internal clock outputs
Number of external clock outputs
Manual clock switchover
Gated lock signal
Clock feedback modes
Control signals
Table 2–4. Cyclone II PLL Features
Feature
Table 2–4
m / (n × post-scale counter)
m and post-scale counter values (C0 to C2) range from 1 to 32. n ranges
from 1 to 4.
Cyclone II PLLs have an advanced clock shift capability that enables
programmable phase shifts in increments of at least 45°. The finest
resolution of phase shifting is determined by the voltage control oscillator
(VCO) period divided by 8 (for example, 1/1000 MHz/8 = down to 125-ps
increments).
The programmable duty cycle allows PLLs to generate clock outputs with
a variable duty cycle. This feature is supported on each PLL post-scale
counter (C0-C2).
The Cyclone II PLL has three outputs which can drive the global clock
network. One of these outputs (C2) can also drive a dedicated
PLL
The C2 output drives a dedicated
used to drive an external clock output, it can be used to drive the internal
global clock network. The C2 output can concurrently drive the external
clock output and internal global clock network.
The Cyclone II PLLs support manual switchover of the reference clock
through internal logic. This enables you to switch between two reference
input clocks during user mode for applications that may require clock
redundancy or support for clocks with two different frequencies.
The lock output indicates that there is a stable clock output signal in phase
with the reference clock. Cyclone II PLLs include a programmable counter
that holds the lock signal low for a user-selected number of input clock
transitions, allowing the PLL to lock before enabling the locked signal.
Either a gated locked signal or an ungated locked signal from the locked
port can drive internal logic or an output pin.
In zero delay buffer mode, the external clock output pin is phase-aligned
with the clock input pin for zero delay.
In normal mode, the PLL compensates for the internal global clock network
delay from the input clock pin to the clock port of the IOE output registers
or registers in the logic array.
In no compensation mode, the PLL does not compensate for any clock
networks.
The
The areset signal resets/resynchronizes the inputs for each PLL.
The pfdena signal controls the phase frequency detector (PFD) output
with a programmable gate.
describes the PLL features in Cyclone II devices.
<#>
pllenable
_OUT
pin (single ended or differential).
signal enables and disables the PLLs.
Description
PLL
<#>
_OUT
pin. If the C2 output is not
Altera Corporation
February 2007