ADSP-2195MKST-160 Analog Devices Inc, ADSP-2195MKST-160 Datasheet - Page 44
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ADSP-2195MKST-160
Manufacturer Part Number
ADSP-2195MKST-160
Description
IC DSP CONTROLLER 16BIT 144LQFP
Manufacturer
Analog Devices Inc
Series
ADSP-21xxr
Type
Fixed Pointr
Datasheet
1.ADSP-2195MKST-160.pdf
(68 pages)
Specifications of ADSP-2195MKST-160
Rohs Status
RoHS non-compliant
Interface
Host Interface, SPI, SSP, UART
Clock Rate
160MHz
Non-volatile Memory
ROM (48 kB)
On-chip Ram
80kB
Voltage - I/o
3.30V
Voltage - Core
2.50V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
144-LQFP
Device Core Size
24b
Format
Fixed Point
Clock Freq (max)
160MHz
Mips
160
Device Input Clock Speed
160MHz
Ram Size
32KB
Program Memory Size
48KB
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (min)
2.37V
Operating Supply Voltage (max)
2.63/3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Lead Free Status / Rohs Status
Not Compliant
ADSP-2195
Serial Port (SPORT) Frame Synch Timing
Table 19
To determine whether communication is possible between two devices at clock speed n, the following specifications must
be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3)
R/TCLK width.
Table 19. Serial Port (SPORT) Frame Synch Timing
1
2
3
44
Referenced to drive edge.
MCE = 1, TFS enable and TFS valid follow t
Referenced to sample edge.
Parameter
Switching Characteristics
t
t
t
t
t
t
Timing Requirements
t
t
t
t
HOFSE
HOFSI
DDTENFS
DDTLFSE
DDTE
DDTI
SFSE
SFSI
HDTE
HDTI
and
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
Figure 22
Description
RFS Hold after RCLK (Internally Generated RFS)
TFS Hold after TCLK (Internally Generated TFS)
Data Enable from late FS or MCE = 1, MFD = 0
Data Delay from Late External TFS or External RFS with
MCE = 1, MFD = 0
Transmit Data Hold after TCLK (external clk)
Transmit Data Hold after TCLK (internal clk)
Transmit Data Delay after TCLK (external clk)
Transmit Data Delay after TCLK (internal clk)
TFS/RFS Setup before TCLK/RCLK (external clk)
TFS/RFS Setup before TCLK/RCLK (internal clk)
describe SPORT frame synch operations.
For current information contact Analog Devices at 800/262-5643
3
DDTLFSE
and t
DDTENFS
.
1
1
1
1
2
1
1
3
3
Min
0
0
0
–0.6
–0.6
September 2001
Max
12.4
12.2
4.7
4.7
12.4
12.2
12.2
11.1
TBD
TBD
REV. PrA
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns