ADSP-2195MKST-160 Analog Devices Inc, ADSP-2195MKST-160 Datasheet - Page 38
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ADSP-2195MKST-160
Manufacturer Part Number
ADSP-2195MKST-160
Description
IC DSP CONTROLLER 16BIT 144LQFP
Manufacturer
Analog Devices Inc
Series
ADSP-21xxr
Type
Fixed Pointr
Datasheet
1.ADSP-2195MKST-160.pdf
(68 pages)
Specifications of ADSP-2195MKST-160
Rohs Status
RoHS non-compliant
Interface
Host Interface, SPI, SSP, UART
Clock Rate
160MHz
Non-volatile Memory
ROM (48 kB)
On-chip Ram
80kB
Voltage - I/o
3.30V
Voltage - Core
2.50V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
144-LQFP
Device Core Size
24b
Format
Fixed Point
Clock Freq (max)
160MHz
Mips
160
Device Input Clock Speed
160MHz
Ram Size
32KB
Program Memory Size
48KB
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (min)
2.37V
Operating Supply Voltage (max)
2.63/3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Lead Free Status / Rohs Status
Not Compliant
ADSP-2195
Host Port ALE Mode Read Cycle Timing
Table 16
on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description
Table 16. Host Port ALE Mode Read Cycle Timing
1
38
t
the same time.
Parameter
Switching Characteristics
t
t
t
t
Timing Requirements
t
t
t
t
t
t
t
t
t
t
NH
RHKS
RHKH
RHS
RHH
CSAL
ALCS
RCSW
ALR
RCS
ALPW
HKRD
AALS
ALAH
RDH
are peripheral bus latencies (n t
and
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
Figure 19
Description
HRD asserted to HACK asserted (setup, ACK Mode)
HRD de-asserted to HACK de-asserted (hold, ACK Mode)
HRD asserted to HACK asserted (setup, Ready Mode)
HRD asserted to HACK de-asserted (hold, Ready Mode)
HCMS or HCIOMS asserted to HALE asserted (delay)
HALE de-asserted to optional HCMS or HCIOMS
de-asserted
HRD de-asserted to HCMS or HCIOMS de-asserted
HALE de-asserted to HRD asserted
HRD de-asserted (after last byte) to HCMS or
HCIOMS de-asserted (ready for next read)
HALE asserted pulsewidth
HACK asserted to HRD de-asserted (hold, ACK Mode)
Address valid to HALE de-asserted (setup)
HALE de-asserted to address invalid (hold)
HRD de-asserted to data invalid (hold)
describe host port read operations in Address Latch Enable (ALE) mode. For more information
HCLK
For current information contact Analog Devices at 800/262-5643
); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at
Min
2
0
1
1
1
1
4
1.5
4
1
1
on page
10.
September 2001
Max
2+t
2
2
2+t
NH
NH
1
1
REV. PrA
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns