XC56309AG100A Freescale Semiconductor, XC56309AG100A Datasheet - Page 160

• Manufacturer Part Number: XC56309AG100A
• Description: IC DSP 24BIT 100MHZ 144-TQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of XC56309AG100A

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Synchronous Serial Interface (ESSI)
7.5.4 ESSI Receive Shift Register
The 24-bit Receive Shift Register (see Figure 7-12 and Figure 7-13) receives incoming data
from the serial receive data signal. The selected (internal/external) bit clock shifts data in when
the associated frame sync I/O is asserted. Data is received MSB first if SHFD is cleared and LSB
first if SHFD is set. Data transfers to the ESSI Receive Data Register (RX) after 8, 12, 16, 24, or
32 serial clock cycles are counted, depending on the word length control bits in the CRA.
7.5.5 ESSI Receive Data Register (RX)
The Receive Data Register (RX) is a 24-bit read-only register that accepts data from the receive
shift register as it becomes full, according to Figure 7-12 and Figure 7-13. The data read is
aligned according to the value of the ALC bit. When the ALC bit is cleared, the MSB is bit 23,
and the least significant byte is unused. When the ALC bit is set, the MSB is bit 15, and the most
significant byte is unused. Unused bits are read as 0. If the associated interrupt is enabled, the
DSP is interrupted whenever the RX register becomes full.
7.5.6 ESSI Transmit Shift Registers
The three 24-bit transmit shift registers contain the data being transmitted, as in Figure 7-12 and
Figure 7-13. Data is shifted out to the serial transmit data signals by the selected (whether
internal or external) bit clock when the associated frame sync I/O is asserted. The word-length
control bits in CRA determine the number of bits that must be shifted out before the shift
registers are considered empty and can be written again. Depending on the setting of the CRA,
the number of bits to be shifted out can be 8, 12, 16, 24, or 32. Transmitted data is aligned
according to the value of the ALC bit. When ALC is cleared, the MSB is Bit 23 and the least
significant byte is unused. When ALC is set, the MSB is Bit 15 and the most significant byte is
7-28
Bit Number
1
0
Table 7-5. ESSI Status Register (SSISR) Bit Definitions (Continued)
Bit Name
IF1
IF0
Reset Value
0
0
DSP56309 User’s Manual, Rev. 1
Serial Input Flag 1
The ESSI latches any data on the SC1 signal during reception of the first
received bit after the frame sync is detected. IF1 is updated with this data
when the data in the receive shift register transfers into the receive data
register. IF1 is enabled only when SC1 is an input flag and Synchronous
mode is selected; that is, when SC1 is programmed as ESSI in the port
control register (PCR), the SYN bit is set, and the TE2 and SCD1 bits are
cleared. If it is not enabled, IF1 is cleared.
Serial Input Flag 0
The ESSI latches any data on the SC0 signal during reception of the first
received bit after the frame sync is detected. The IF0 bit is updated with this
data when the data in the receive shift register transfers into the receive
data register. IF0 is enabled only when SC0 is an input flag and the
Synchronous mode is selected; that is, when SC0 is programmed as ESSI
in the port control register (PCR), the SYN bit is set, and the TE1 and SCD0
bits are cleared. If it is not enabled, the IF0 bit is cleared.
Description
Freescale Semiconductor