XC56309AG100A Freescale Semiconductor, XC56309AG100A Datasheet - Page 159

• Manufacturer Part Number: XC56309AG100A
• Description: IC DSP 24BIT 100MHZ 144-TQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of XC56309AG100A

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Bit Number
23–8
7
6
5
4
3
2
Bit Name
ROE
RDF
TDE
TUE
RFS
TFS
Table 7-5. ESSI Status Register (SSISR) Bit Definitions
Reset Value
0
0
0
0
0
0
0
DSP56309 User’s Manual, Rev. 1
Reserved. Write to 0 for future compatibility.
Receive Data Register Full
Set when the contents of the receive shift register transfer to the receive
data register. RDF is cleared when the DSP reads the receive data register.
If RIE and RDF are set, a DSP receive data interrupt request is issued.
Transmit Data Register Empty
Set when the contents of the transmit data register of every enabled
transmitter are transferred to the transmit shift register. It is also set for a
TSR disabled time slot period in Network mode (as if data were being
transmitted after the TSR has been written). When TDE is set, TDE data is
written to all the TX registers of the enabled transmitters or to the TSR. The
TDE bit is cleared when the DSP writes to all the transmit data registers of
the enabled transmitters, or when the DSP writes to the TSR to disable
transmission of the next time slot. If the TIE bit is set, a DSP transmit data
interrupt request is issued when TDE is set.
Receiver Overrun Error Flag
Set when the serial receive shift register is filled and ready to transfer to the
receive data register (RX) but RX is already full (that is, the RDF bit is set).
If the REIE bit is set, a DSP receiver overrun error interrupt request is
issued when the ROE bit is set. The programmer clears ROE by reading
the SSISR with the ROE bit set and then reading the RX.
Transmitter Underrun Error Flag
TUE is set when at least one of the enabled serial transmit shift registers is
empty (that is, there is no new data to be transmitted) and a transmit time
slot occurs. When a transmit underrun error occurs, the previous data
(which is still present in the TX registers not written) is retransmitted. In
Normal mode, there is only one transmit time slot per frame. In Network
mode, there can be up to 32 transmit time slots per frame. If the TEIE bit is
set, a DSP transmit underrun error interrupt request is issued when the
TUE bit is set. The programmer can also clear TUE by first reading the
SSISR with the TUE bit set, then writing to all the enabled transmit data
registers or to the TSR.
Receive Frame Sync Flag
When set, the RFS bit indicates that a receive frame sync occurred during
the reception of a word in the serial receive data register. In other words,
the data word is from the first time slot in the frame. When the RFS bit is
cleared and a word is received, it indicates (only in Network mode) that the
frame sync did not occur during reception of that word. RFS is valid only if
the receiver is enabled (that is, if the RE bit is set). In Normal mode, RFS is
always read as 1 when data is read because there is only one time slot per
frame, the frame sync time slot.
Transmit Frame Sync Flag
When set, TFS indicates that a transmit frame sync occurred in the current
time slot. TFS is set at the start of the first time slot in the frame and cleared
during all other time slots. If the transmitter is enabled, data written to a
transmit data register during the time slot when TFS is set is transmitted (in
Network mode) during the second time slot in the frame. TFS is useful in
Network mode to identify the start of a frame. TFS is valid only if at least
one transmitter is enabled that is, when TE0, TE1, or TE2 is set). In Normal
mode, TFS is always read as 1 when data is being transmitted because
there is only one time slot per frame, the frame sync time slot.
Description
ESSI Programming Model
7-27