XC56309AG100A Freescale Semiconductor, XC56309AG100A Datasheet - Page 114

• Manufacturer Part Number: XC56309AG100A
• Description: IC DSP 24BIT 100MHZ 144-TQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of XC56309AG100A

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Host Interface (HI08)
6.6.3 Host Data Direction Register (HDDR)
The HDDR controls the direction of the data flow for each of the HI08 signals configured as
GPIO. Even when the HI08 functions as the host interface, its unused signals can be configured
as GPIO signals. For information on the HI08 GPIO configuration options, see Section 6.2, Host
Port Signals, on page 6-3. If Bit DRxx is set, the corresponding HI08 signal is configured as an
output signal. If Bit DRxx is cleared, the corresponding HI08 signal is configured as an input
signal. Hardware and software reset clear the HDDR bits.
6-14
Bit Number
DR15 DR14 DR13 DR12 DR11 DR10 DR9
15
4–3
2
1
0
14
Table 6-9. Host Status Register (HSR) Bit Definitions (Continued)
Figure 6-8. Host Data Direction Register (HDDR) (X:$FFFFC8)
13
Bit Name
HF[1–0]
HRDF
HTDE
HCP
12
Reset Value
11
0
0
0
0
10
DSP56309 User’s Manual, Rev. 1
Host Flags 0, 1
General-purpose flags for host-to-DSP communication. These bits reflect
the status of host flags HF[1–0] in the ICR on the host side. These two
general-purpose flags can be used individually or as encoded pairs in a
simple host-to-DSP communication protocol, implemented in both the
DSP and the host processor software.
Host Command Pending
Reflects the status of the CVR[HC] bit. When set, it indicates that a host
command interrupt is pending. HI08 hardware clears HC and HCP when
the DSP core services the interrupt request. If the host clears HC, HCP is
also cleared.
Host Transmit Data Empty
Indicates that the host transmit data register (HTX) is empty and can be
written by the DSP core. HTDE is set when the HTX register is transferred
to the RXH:RXM:RXL registers. The host processor can also set HTDE
using the initialize function. HTDE is cleared when the DSP core writes to
HTX.
Host Receive Data Full
Indicates that the host receive data register (HRX) contains data from the
host processor. HRDF is set when data is transferred from the
TXH:TXM:TXL registers to the HRX register. The host processor can also
clear HRDF using the initialize function.
9
DR8
8
DR7
7
DR6
6
DR5
Description
5
DR4
4
DR3
3
Freescale Semiconductor
DR2
2
DR1
1
DR0
0