XC56309AG100A Freescale Semiconductor, XC56309AG100A Datasheet - Page 123

• Manufacturer Part Number: XC56309AG100A
• Description: IC DSP 24BIT 100MHZ 144-TQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of XC56309AG100A

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Bit Number
6
5
4
3
2
1
0
Table 6-15. Interface Control Register (ICR) Bit Definitions (Continued)
Bit Name
HLEND
HDRQ
RREQ
TREQ
HF1
HF0
Reset Value
0
0
0
0
0
0
0
DSP56309 User’s Manual, Rev. 1
Reserved. Write to 0 for future compatibility.
Host Little Endian
If the HLEND bit is cleared, the host can access the HI08 in Big-Endian byte
order. If set, the host can access the HI08 in Little-Endian byte order. If the
HLEND bit is cleared the RXH/TXH register is located at address $5, the
RXM/TXM register at $6, and the RXL/TXL register at $7. If the HLEND bit is
set, the RXH/TXH register is located at address $7, the RXM/TXM register at
$6, and the RXL/TXL register at $5.
Host Flag 1
A general-purpose flag for host-to-DSP communication. The host processor
can set or clear HF1, and the DSP56309 can not change it. HF1 is reflected
in the HSR on the DSP side of the HI08.
Host Flag 0
A general-purpose flag for host-to-DSP communication. The host processor
can set or clear HF0, and the DSP56309 cannot change it. HF0 is reflected in
the HSR on the DSP side of the HI08.
Double Host Request
If cleared, the HDRQ bit configures HREQ/HTRQ and HACK/HRRQ as
HREQ and HACK, respectively. If HDRQ is set, HREQ/HTRQ is configured
as HTRQ, and HACK/HRRQ is configured as HRRQ.
Transmit Request Enable
Enables host requests via the host request (HREQ or HTRQ) signal when the
transmit data register empty (TXDE) status bit in the ISR is set. If TREQ is
cleared, TXDE interrupts are disabled. If TREQ and TXDE are set, the host
request signal is asserted.
Receive Request Enable
Controls the HREQ signal for host receive data transfers. RREQ enables host
requests via the host request (HREQ or HRRQ) signal when the receive data
register full (RXDF) status bit in the ISR is set. If RREQ is cleared, RXDF
interrupts are disabled. If RREQ and RXDF are set, the host request signal
(HREQ or HRRQ) is asserted.
TREQ
TREQ
0
0
1
1
0
0
1
1
RREQ
RREQ
TREQ and RREQ modes (HDRQ = 0)
TREQ and RREQ modes (HDRQ = 1)
0
1
0
1
0
1
0
1
HTRQ Signal
No interrupts (polling)
No interrupts (polling)
Description
RXDF and TXDE request (interrupts)
TXDE request
TXDE request
(interrupt)
(interrupt)
RXDF request (interrupt)
TXDE request (interrupt)
No interrupts (polling)
HREQ Signal
Host Programmer Model
RXDF request
RXDF request
HRRQ Signal
No interrupts
No interrupts
(interrupt)
(interrupt)
(polling)
(polling)
6-23