ADSP-2196MKSTZ-160 Analog Devices Inc, ADSP-2196MKSTZ-160 Datasheet - Page 16

• Manufacturer Part Number: ADSP-2196MKSTZ-160
• Description: IC DSP CONTROLLER 16BIT 144-LQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2196MKSTZ-160

• Interface: Host Interface, SPI, SSP, UART
• Clock Rate: 160MHz
• Non-volatile Memory: ROM (48 kB)
• On-chip Ram: 40kB
• Voltage - I/o: 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 16b
• Format: Fixed Point
• Clock Freq (max): 160MHz
• Mips: 160
• Device Input Clock Speed: 160MHz
• Ram Size: 40KB
• Program Memory Size: 48KB
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (min): 2.37V
• Operating Supply Voltage (max): 2.63/3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-2196
• Boot from SPI, up to 4K bits—The SPI0 port uses the
• Boot from SPI, from >4K bits to 512K bits—The SPI0
Bus Request and Bus Grant
The ADSP-2196 can relinquish control of the data and
address buses to an external device. When the external
device requires access to the bus, it asserts the bus request
(BR) signal. The (BR) signal is arbitrated with core and
peripheral requests. External Bus requests have the lowest
priority. If no other internal request is pending, the external
bus request will be granted. Due to synchronizer and arbi-
tration delays, bus grants will be provided with a minimum
of three peripheral clock delays. The ADSP-2196 will
respond to the bus grant by:
• Three-stating the data and address buses and the MS3–0,
• Asserting the bus grant (BG) signal.
The ADSP-2196 will halt program execution if the bus is
granted to an external device and an instruction fetch or
data read/write request is made to external general-purpose
or peripheral memory spaces. If an instruction requires two
external memory read accesses, the bus will not be granted
between the two accesses. If an instruction requires an
external memory read and an external memory write access,
the bus may be granted between the two accesses. The
external memory interface can be configured so that the
core will have exclusive use of the interface. DMA and Bus
Requests will be granted. When the external device releases
BR, the DSP releases BG and continues program execution
from the point at which it stopped.
The bus request feature operates at all times, even while the
DSP is booting and RESET is active.
16
SPI0SEL1 (reconfigured PF2) output pin to select a
single serial EPROM device, submits a read command at
address 0x00, and begins clocking consecutive data into
internal or external memory. Use only SPI-compatible
EPROMs of 4K bit (12-bit address range). The SPI0
boot routine located in internal ROM memory space
executes a boot-stream-formatted program, using the top
16 locations of Page 0 program memory and the top 272
locations of Page 0 data memory. The SPI boot configu-
ration is SPIBAUD0=60 (decimal), CPHA=1, CPOL=1,
8-bit data, and MSB first.
port uses the SPI0SEL1 (re-configured PF2) output pin
to select a single serial EPROM device, submits a read
command at address 0x00, and begins clocking consecu-
tive data into internal or external memory. Use only
SPI-compatible EPROMs of 4K bit (16-bit address
range). The SPI0 boot routine located in internal ROM
memory space executes a boot-stream-formatted
program, using the top 16 locations of Page 0 program
memory and the top 272 locations of Page 0 data memory.
BMS, IOMS, RD, and WR output drivers.
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
For current information contact Analog Devices at 800/262-5643
The ADSP-2196 asserts the BGH pin when it is ready to
start another external port access, but is held off because
the bus was previously granted. This mechanism can be
extended to define more complex arbitration protocols for
implementing more elaborate multimaster systems.
Instruction Set Description
The ADSP-2196 assembly language instruction set has an
algebraic syntax that was designed for ease of coding and
readability. The assembly language, which takes full
advantage of the processor’s unique architecture, offers the
following benefits:
• ADSP-219x assembly language syntax is a superset of and
• The algebraic syntax eliminates the need to remember
• Every instruction, but two, assembles into a single, 24-bit
• Multifunction instructions allow parallel execution of an
• Program flow instructions support a wider variety of con-
Development Tools
The ADSP-2196 is supported with a complete set of
software and hardware development tools, including Analog
Devices’ emulators and VisualDSP++® development envi-
ronment. The same emulator hardware that supports other
ADSP-219x DSPs, also fully emulates the ADSP-2196.
The VisualDSP++ project management environment lets
programmers develop and debug an application. This envi-
ronment includes an easy-to-use assembler that is based on
an algebraic syntax; an archiver (librarian/library builder),
a linker, a loader, a cycle-accurate instruction-level simula-
source-code-compatible (except for two data registers
and DAG base address registers) with ADSP-218x family
syntax. It may be necessary to restructure ADSP-218x
programs to accommodate the ADSP-2196’s unified
memory space and to conform to its interrupt vector map.
cryptic assembler mnemonics. For example, a typical
arithmetic add instruction, such as AR = AX0 + AY0,
resembles a simple equation.
word that can execute in a single instruction cycle. The
exceptions are two dual word instructions. One writes 16-
or 24-bit immediate data to memory, and the other is an
absolute jump/call with the 24-bit address specified in the
instruction.
arithmetic, MAC, or shift instruction with up to two
fetches or one write to processor memory space during a
single instruction cycle.
ditional and unconditional jumps/calls and a larger set of
conditions on which to base execution of conditional
instructions.
September 2001
REV. PrA