ADSP-BF527KBCZ-6C2 Analog Devices Inc, ADSP-BF527KBCZ-6C2 Datasheet - Page 52

• Manufacturer Part Number: ADSP-BF527KBCZ-6C2
• Description: IC DSP 16BIT 600MHZ 289CSPBGA
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF527KBCZ-6C2

• Package / Case: 289-CSPBGA
• Interface: DMA, Ethernet, I²C, PPI, SPI, SPORT, UART, USB
• Clock Rate: 600MHz
• Non-volatile Memory: ROM (32 kB)
• On-chip Ram: 132kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.10V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Svhc: No SVHC (18-Jun-2010)
• Cache On Chip L1/l2 Memory: 48KB
• Core Frequency Typ: 600MHz
• Dsp Type: Core
• External Supported Memory: SDRAM, SRAM, FLASH, ROM
• Interface Type: SPI, Parallel, 2 Wire
• Rohs Compliant: Yes
• Mmac: 1200
• No. Of Pins: 289
• Package: 289CSP-BGA
• Maximum Speed: 600 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-BF527-MPSKIT - BOARD EVAL MEDIA PLAYER BF527ADZS-BF527-EZLITE - BOARD EVAL ADSP-BF527
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Serial Ports
Table 42
through
Table 42. Serial Ports—External Clock
1
2
3
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
Referenced to sample edge.
Verified in design but untested.
Referenced to drive edge.
SFSE
HFSE
SDRE
HDRE
SCLKEW
SCLKE
SUDTE
SUDRE
DFSE
HOFSE
DDTE
HDTE
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
TFSx/RFSx Setup Before TSCLKx
RSCLKx
TFSx/RFSx Hold After TSCLKx/RSCLKx
Receive Data Setup Before RSCLKx
Receive Data Hold After RSCLKx
TSCLKx/RSCLKx Width
TSCLKx/RSCLKx Period
Start-Up Delay From SPORT Enable To
First External TFSx
Start-Up Delay From SPORT Enable To
First External RFSx
TFSx/RFSx Delay After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)
TFSx/RFSx Hold After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)
Transmit Data Delay After TSCLKx
Transmit Data Hold After TSCLKx
Figure 27 on Page 56
through
1
Table 46 on Page 56
2
2
describe serial port operations.
and
1
3
3
3
3
1
Figure 24 on Page 54
1
Min
3.0
3.0
3.0
3.5
7.0
2.0 × t
4.0 × t
4.0 × t
0.0
0.0
1.8V Nominal
Rev. B | Page 52 of 88 | May 2010
SCLK
SCLKE
SCLKE
ADSP-BF522/ADSP-BF524/
V
DDEXT
Max
10.0
10.0
ADSP-BF526
Min
3.0
3.0
3.0
3.0
4.5
2.0 × t
4.0 × t
4.0 × t
0.0
0.0
2.5/3.3V Nominal
SCLK
SCLKE
SCLKE
V
DDEXT
Max
10.0
10.0
Min
3.0
3.0
3.0
3.5
2.0 × t
4.0 × t
4.0 × t
0.0
0.0
7.0
1.8V Nominal
SCLK
SCLKE
SCLKE
ADSP-BF523/ADSP-BF525/
V
DDEXT
Max
10.0
10.0
ADSP-BF527
Min
3.0
3.0
3.0
3.0
2.0 × t
4.0 × t
4.0 × t
0.0
0.0
4.5
2.5/3.3V Nominal
SCLK
SCLKE
SCLKE
V
DDEXT
Max
10.0
10.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns