ADSP-BF527KBCZ-6C2 Analog Devices Inc, ADSP-BF527KBCZ-6C2 Datasheet - Page 46

• Manufacturer Part Number: ADSP-BF527KBCZ-6C2
• Description: IC DSP 16BIT 600MHZ 289CSPBGA
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF527KBCZ-6C2

• Package / Case: 289-CSPBGA
• Interface: DMA, Ethernet, I²C, PPI, SPI, SPORT, UART, USB
• Clock Rate: 600MHz
• Non-volatile Memory: ROM (32 kB)
• On-chip Ram: 132kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.10V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Svhc: No SVHC (18-Jun-2010)
• Cache On Chip L1/l2 Memory: 48KB
• Core Frequency Typ: 600MHz
• Dsp Type: Core
• External Supported Memory: SDRAM, SRAM, FLASH, ROM
• Interface Type: SPI, Parallel, 2 Wire
• Rohs Compliant: Yes
• Mmac: 1200
• No. Of Pins: 289
• Package: 289CSP-BGA
• Maximum Speed: 600 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-BF527-MPSKIT - BOARD EVAL MEDIA PLAYER BF527ADZS-BF527-EZLITE - BOARD EVAL ADSP-BF527
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SDRAM Interface Timing
Table 36. SDRAM Interface Timing for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors
1
2
Table 37. SDRAM Interface Timing for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors
1
2
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
The t
Command balls include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
The t
Command balls include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
SSDAT
HSDAT
SCLK
SCLKH
SCLKL
DCAD
HCAD
DSDAT
ENSDAT
SSDAT
HSDAT
SCLK
SCLKH
SCLKL
DCAD
HCAD
DSDAT
ENSDAT
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
SCLK
SCLK
value is the inverse of the f
value is the inverse of the f
Data Setup Before CLKOUT
Data Hold After CLKOUT
CLKOUT Period
CLKOUT Width High
CLKOUT Width Low
Command, Address, Data Delay After CLKOUT
Command, Address, Data Hold After CLKOUT
Data Disable After CLKOUT
Data Enable After CLKOUT
Data Setup Before CLKOUT
Data Hold After CLKOUT
CLKOUT Period
CLKOUT Width High
CLKOUT Width Low
Command, Address, Data Delay After CLKOUT
Command, Address, Data Hold After CLKOUT
Data Disable After CLKOUT
Data Enable After CLKOUT
SCLK
SCLK
specification discussed in
specification discussed in
1
1
Rev. B | Page 46 of 88 | May 2010
Table 14
Table 14
and
and
2
Table
Table
2
2
2
17. Package type and reduced supply voltages affect the best-case values listed here.
17. Package type and reduced supply voltages affect the best-case values listed here.
Min
1.5
1.0
10
2.5
2.5
1.0
0.0
1.8V Nominal
V
DDMEM
Min
1.5
1.3
12.5
5.0
5.0
1.0
0.0
Max
4.0
5.0
1.8V Nominal
V
DDMEM
Max
5.0
5.5
Min
1.5
0.8
7.5
2.5
2.5
1.0
0.0
2.5/3.3V Nominal
Min
1.5
0.8
10
4.0
4.0
1.0
0.0
2.5/3.3V Nominal
V
DDMEM
V
Max
4.0
4.0
DDMEM
Max
4.0
5.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns