DSPB56362AG120 Freescale Semiconductor, DSPB56362AG120 Datasheet - Page 85

• Manufacturer Part Number: DSPB56362AG120
• Description: IC DSP 24BIT AUD 120MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56362AG120

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 120MHz
• Non-volatile Memory: ROM (126 kB)
• On-chip Ram: 42kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 120MHz
• Mips: 120
• Device Input Clock Speed: 120MHz
• Ram Size: 42KB
• Program Memory Size: 90KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.46V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Product: DSPs
• Data Bus Width: 24 bit
• Processor Series: DSP563xx
• Core: 56000
• Numeric And Arithmetic Format: Fixed-Point
• Instruction Set Architecture: Modified Harvard
• Device Million Instructions Per Second: 120 MIPS
• Maximum Clock Frequency: 120 MHz
• Program Memory Type: Flash
• Data Ram Size: 42 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: SPI, I2C, ESAI, SHI
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.13
Freescale Semiconductor
171
172
173
174
175
176
177
178
179
180
181
182
183
184
186
No.
Tolerable spike width on SCL or SDA
Filters bypassed
Narrow filters enabled
Wide filters enabled
SCL clock frequency
Bus free time
Start condition set-up time
Start condition hold time
SCL low period
SCL high period
SCL and SDA rise time
SCL and SDA fall time
Data set-up time
Data hold time
Stop condition set-up time
Capacitive load for each line
DSP clock frequency
Filters bypassed
Narrow filters enabled
Wide filters enabled
HREQ in deassertion to last SCL edge
(HREQ in set-up time)
First SCL sampling edge to HREQ output
deassertion
Filters bypassed
Narrow filters enabled
Wide filters enabled
Serial Host Interface (SHI) I
Characteristics
Table 3-22 SHI I
DSP56362 Technical Data, Rev. 4
Standard I
2
2
Expression
2
×
×
Symbol/
T
T
×
T
T
T
T
t
T
NG;RQO
2
SU;RQI
T
SU;STO
F
T
SU;STA
HD;STA
SU;DAT
HD;DAT
F
T
T
T
HIGH
C Protocol Timing
T R
LOW
C
—
BUF
DSP
C
2
SCL
T F
C
C
C Protocol Timing
b
+ 120
+ 208
+ 30
2
C*
10.6
11.8
13.1
Min
250
4.7
4.7
4.0
4.7
4.0
0.0
4.0
0.0
—
—
—
—
—
—
—
—
—
—
Standard
Serial Host Interface (SHI) I
1000
Max
100
100
300
400
140
228
50
50
—
—
—
—
—
—
—
—
—
—
—
—
0
20 + 0.1
20 + 0.1
28.5
39.7
61.0
Min
100
1.3
0.6
0.6
1.3
1.3
0.0
0.6
0.0
—
—
—
—
—
—
—
—
Fast-Mode
×
×
C
C
b
b
2
C Protocol Timing
Max
100
400
300
300
400
140
228
0.9
50
—
—
—
—
—
—
—
—
—
—
—
50
0
MHz
Unit
kHz
pF
ns
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
ns
ns
3-59