XC95288XV-7CS280C Xilinx Inc, XC95288XV-7CS280C Datasheet - Page 4

• Manufacturer Part Number: XC95288XV-7CS280C
• Description: IC CPLD 2.5V ISP 280-CSP
• Manufacturer: Xilinx Inc
• Series: XC9500XVr

Specifications of XC95288XV-7CS280C

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 2.37 V ~ 2.62 V
• Number Of Logic Elements/blocks: 16
• Number Of Macrocells: 288
• Number Of Gates: 6400
• Number Of I /o: 192
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 280-CSBGA
• Voltage: 2.5V
• Memory Type: FLASH
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -

XC9500XV Family High-Performance CPLD
Macrocell
Each XC9500XV macrocell may be individually configured
for a combinatorial or registered function. The macrocell
and associated FB logic is shown in
Five direct product terms from the AND-array are available
for use as primary data inputs (to the OR and XOR gates) to
implement combinatorial functions, or as control inputs
including clock, clock enable, set/reset, and output enable.
4
Fast CONNECT II
Switch Matrix
From
54
Figure
Programmable
AND-Array
Figure 2: XC9500XV Function Block
3.
www.xilinx.com
Allocators
Product
Term
Set/Reset
The product term allocator associated with each macrocell
selects how the five direct terms are used.
The macrocell register can be configured as a D-type or
T-type flip-flop, or it may be bypassed for combinatorial
operation. Each register supports both asynchronous set
and reset operations. During power-up, all user registers
are initialized to the user-defined preload state (default to 0
if unspecified).
Global
Macrocell 18
1
Macrocell 1
Clocks
Global
3
18
18
18
OUT
To Fast CONNECT II
Switch Matrix
PTOE
DS049 (v3.0) June 25, 2007
Product Specification
To I/O Blocks
DS049_02_041400
R