XC95288XV-7CS280C Xilinx Inc, XC95288XV-7CS280C Datasheet - Page 12

• Manufacturer Part Number: XC95288XV-7CS280C
• Description: IC CPLD 2.5V ISP 280-CSP
• Manufacturer: Xilinx Inc
• Series: XC9500XVr

Specifications of XC95288XV-7CS280C

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 2.37 V ~ 2.62 V
• Number Of Logic Elements/blocks: 16
• Number Of Macrocells: 288
• Number Of Gates: 6400
• Number Of I /o: 192
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 280-CSBGA
• Voltage: 2.5V
• Memory Type: FLASH
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -

XC9500XV Family High-Performance CPLD
The input buffer is compatible with 3.3V CMOS and 2.5V
CMOS signals. The input buffer uses the internal 2.5V volt-
age supply (V
constant and do not vary with the V
buffer provides input hysteresis (50 mV typical) to help
reduce system noise for input signals with slow rise or fall
edges.
Each output driver is designed to provide fast switching with
minimal power noise. All output drivers in the device may be
configured for driving either 3.3V, 2.5V, or 1.8V CMOS lev-
els by connecting the device output voltage supply (V
to a 3.3V, 2.5V, or 1.8V voltage supply.
how the XC9500XV device can be used in a 2.5V only sys-
tem.
Each output driver can also be configured for slew-rate lim-
ited operation. Output edge rates may be slowed down to
reduce system noise (with an additional time delay of
T
The output enable may be generated from one of four
options: a product term signal from the macrocell, any of the
global output enable signals (GTS), always “1”, or always
“0”. There are two global output enables for devices with 72
or fewer macrocells, and four global output enables for
devices with 144 or more macrocells. Any selected output
enable signal may be inverted locally at each pin output to
provide maximum design flexibility.
12
SLEW
3.3V CMOS or
2.5V CMOS
) under user control. See
3.3V
2.5V
0V
0V
CCINT
Figure 11: XC9500XV Devices in (a) 2.5V only and (b) Mixed 3.3V/2.5V/1.8V Systems
) to ensure that the input thresholds are
IN
V
2.5V
CCINT
XC9500XV
CPLD
GND
(a)
Figure
V
V
CCIO1
CCIO2
OUT
CCIO
12.
Figure 11(a)
voltage. Each input
2.5V CMOS
2.5V
0V
shows
www.xilinx.com
CCIO
)
3.3V CMOS or
2.5V CMOS
Each IOB provides user programmable ground pin capabil-
ity. This allows device I/O pins to be configured as additional
ground pins in order to force otherwise unused pins to a low
voltage state, as well as provide for additional device
grounding capability. This grounding of the pin is achieved
by internal logic that forces a logic Low output regardless of
the internal macrocell signal, so the internal macrocell logic
is unaffected by the programmable ground pin capability.
Each IOB also provides for bus-hold circuitry that is active
during valid user operation. The bus-hold feature eliminates
the need to tie unused pins either High or Low by holding
the last known state of the input until the next input signal is
present. The bus-hold circuit drives back the same state via
a nominal resistance (R
Note: The bus-hold output will drive no higher than V
prevent overdriving signals when interfacing to 2.5V com-
ponents.
When the device is not in valid user operation, the bus-hold
circuit defaults to an equivalent 50K ohm pull-up resistor in
order to provide a known repeatable device state. This
occurs when the device is in the erased state, in program-
ming mode, in JTAG INTEST mode, or during initial
power-up. A pull-down resistor (1K ohm) may be externally
added to any pin to override the default R
force a Low state during power-up or any of these other
modes.
3.3V
2.5V
0V
0V
V
IN
2.5V
CCINT
XC9500XV
V
1.8V
BH
CCIO1
CPLD
GND
(b)
) of 50K ohms. See
V
3.3V
OUT1
OUT2
CCIO2
DS049 (v3.0) June 25, 2007
Product Specification
1.8V CMOS
3.3V CMOS
2.5V CMOS
DS049_11_051702
BH
3.3V
1.8V
2.5V
resistance to
0V
Figure
0V
0V
CCIO
13.
to
R